A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

This disclosure describes techniques for synchronizing independent data streams. In some instances, a computing device couples to multiple independent sensors, such as cameras, and applies accurate timestamp information to the individual frames of sensor data from the independent sensors. After aligning these data streams by applying these accurate timestamps, the computing device may, in some instances, encode and transmit these timestamped data streams to one or more entities for further processing. In one example, a first camera (e.g., a depth camera configured to generate a depth map) may capture images of an environment, as may a second camera (e.g., an Red-Green-Blue (RGB) camera configured to generate color images). The resulting images may be temporally aligned with one another via the timestamping, and the resulting aligned images from both the depth sensor and the RGB camera may be used to create a three-dimensional (3D) model of the environment.

A high-speed video system is disclosed that includes a moving image absorbing disk at an image plane. The disk has a pattern that passes and blocks image data. The disk is located between an event and an image sensor, or reflects an image to the image sensor. The disk is rotated at a speed that matches the desired reconstructed image frame rate. The image sensor frame data is processed using image reconstruction techniques, such as the D-AMP or TWIST algorithm, to recover a time sequence of reconstructed images. Additional images can be reconstructed for each image sensor frame if some spatial resolution is sacrificed. For continuous video, the disk speed is adjusted to the sensor frame rate. For burst mode, a single sensor image is acquired and a short image sequence is reconstructed. This image capture system works with a variety of radiations, including infrared, light, UV and X-rays.

An image output synchronization method, performed by a programmable logic circuit connected to an oscillator, includes: configuring a count value according to a designated frame rate and a frequency of the oscillator generating a count signal by each one of a plurality of frame controllers; generating a synchronization signal periodically and outputting the synchronization signal to the frame controllers by a clock generator; and performing a synchronization procedure on a camera by each one of the frame controllers when triggered by the synchronization signal every time, with the synchronization procedure including: triggered by the count signal of the oscillator to control a frame control signal outputted to the camera according to the count value and a width of the count signal.

A high-speed video system is disclosed that includes a moving image absorbing disk at an image plane. The disk has a pattern that passes and blocks image data. The disk is located between an event and an image sensor, or reflects an image to the image sensor. The disk is rotated at a speed that matches the desired reconstructed image frame rate. The image sensor frame data is processed using image reconstruction techniques, such as the D-AMP or TWIST algorithm, to recover a time sequence of reconstructed images. Additional images can be reconstructed for each image sensor frame if some spatial resolution is sacrificed. For continuous video, the disk speed is adjusted to the sensor frame rate. For burst mode, a single sensor image is acquired and a short image sequence is reconstructed. This image capture system works with a variety of radiations, including infrared, light, UV and X-rays.

An image output synchronization method, performed by a programmable logic circuit connected to an oscillator, includes: configuring a count value according to a designated frame rate and a frequency of the oscillator generating a count signal by each one of a plurality of frame controllers; generating a synchronization signal periodically and outputting the synchronization signal to the frame controllers by a clock generator; and performing a synchronization procedure on a camera by each one of the frame controllers when triggered by the synchronization signal every time, with the synchronization procedure including: triggered by the count signal of the oscillator to control a frame control signal outputted to the camera according to the count value and a width of the count signal.