Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.

In order to eliminate timing offset between reproduction devices when a content transmitted from a distribution device is received and reproduced by a plurality of reproduction devices, data (SCR) indicating the elapsed time from the start of the content, generated by counting clock pulses, and data (FCR) indicating a frame number generated by counting the number of frames reproduced by a decoder (54) are transmitted by the distribution device, and a clock generation unit (103) in each reproduction device is controlled so that data (STC) indicating the elapsed time and data (FTC) indicating the frame number, which are generated in the same manner by each reproduction device, match the transmitted data (SCR, FCR). Synchronization between reproduction devices can thereby be established even when, in a state in which a content is being reproduced by one reproduction device, another reproduction device subsequently connects to the distribution device.

A system for at least substantially plesiochronously operating a receiver in communication with a plurality of cameras (e.g., at least two plesiochronously operational cameras) is described. In one or more implementations, the system includes a plurality of cameras. Each camera is configured to generate a signal for transmission via a communications link, and the signal comprises data packets encoded in a forward channel. The system also includes a receiver communicatively coupled to the plurality of cameras via the single-ended communications link. The receiver is configured to generate a synchronization data based upon at least one of the data packets. The receiver is also configured to modulate the signal to encode the synchronization data in a reverse channel so that the signal comprises the forward channel data and the reverse channel data simultaneously.

A display driver for a display device including a sync extraction circuit configured to generate a vertical sync source signal in response to a vertical sync period start instruction indicating a start of a vertical sync period, a timing generator configured to generate an internal vertical sync signal in response to the vertical sync source signal; and a drive circuit configured to drive the display panel in synchronization with the internal vertical sync signal.

A data transmitting and receiving device includes: a data transmitting circuit transmitting a clock signal and a data signal synchronized to the clock signal; and a data receiving circuit receiving the clock signal and the data signal; wherein: the data receiving circuit includes a phase error detection circuit detecting a phase error between the data signal and the clock signal; and the data transmitting circuit includes a phase adjusting circuit adjusting a phase of at least one of the clock signal and the data signal based on the phase error.

Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.

A display driver for a display device including a sync extraction circuit configured to generate a vertical sync source signal in response to a vertical sync period start instruction indicating a start of a vertical sync period, a timing generator configured to generate an internal vertical sync signal in response to the vertical sync source signal; and a drive circuit configured to drive the display panel in synchronization with the internal vertical sync signal

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.