Provided is an image processing apparatus for correcting blinking defect noise included in image data generated by an image sensor, the image sensor including pixels arranged two-dimensionally and read-out circuits configured to read out a pixel value. The image processing apparatus is configured to: acquire noise information that associates the pixel value with positional information of the read-out circuits or positional information of each of the pixels, and with feature data related to blinking defect noise attributed to the read-out circuits; determine whether the blinking defect noise occurs on a pixel of interest based on the noise information; calculate candidate values indicating a correction amount for correcting the blinking defect noise based on the noise information and a pixel value of the pixel of interest if the blinking defect noise occurs; and correct the pixel value of the pixel of interest based on the candidate values.

Provided is an image processing apparatus for correcting blinking defect noise included in image data generated by an image sensor, the image sensor including pixels arranged two-dimensionally and read-out circuits configured to read out a pixel value. The image processing apparatus is configured to: acquire noise information that associates the pixel value with positional information of the read-out circuits or positional information of each of the pixels, and with feature data related to blinking defect noise attributed to the read-out circuits; determine whether the blinking defect noise occurs on a pixel of interest based on the noise information; calculate candidate values indicating a correction amount for correcting the blinking defect noise based on the noise information and a pixel value of the pixel of interest if the blinking defect noise occurs; and correct the pixel value of the pixel of interest based on the candidate values.

An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.

An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.

A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

A method of processing a sequence of coded video frames conveyed by a digital data stream, where each frame represents an image, includes receiving the sequence of coded video frames at a recording device, determining a frame interval between presentation of an ith coded frame of the sequence and an (i+1)th coded frame of the sequence, calculating a stream time stamp for the ith coded frame, and calculating a stream time stamp for the (i+1)th coded video frame based on the stream time stamp for the ith coded video frame and the previously determined frame interval.

A method of processing a sequence of coded video frames conveyed by a digital data stream, where each frame represents an image, includes receiving the sequence of coded video frames at a recording device, determining a frame interval between presentation of an ith coded frame of the sequence and an (i+1)th coded frame of the sequence, calculating a stream time stamp for the ith coded frame, and calculating a stream time stamp for the (i+1)th coded video frame based on the stream time stamp for the ith coded video frame and the previously determined frame interval.