A wireless transmission controller device is proposed. The device includes: a signal transmitter configured to receive an image signal input from a USB Type-C or a DP port, which are connected to an image storage device, convert the received image signal into a form of a high-speed serial signal, and wirelessly transmits the converted image signal to a signal receiver by ultra-high frequency communication; and the signal receiver configured to receive a high-speed serial signal from the signal transmitter, undergo a conversion process, and transmit the image signal to an image display device such as a monitor or a smartphone connected to the DP port, wherein, through making the USB Type-C or the Display Port to be wireless, high-speed wireless transmission in real time for a video is possible without a wired cable connection.

A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing, section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-convert d are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

A frame buffer having a size of one video frame of a video stream is provided. The video stream has a source frame rate. Image data units of the video stream are written consecutively to the frame buffer in accordance with a circular buffering scheme and in real-time response to the video stream. Image data units are read from the frame buffer in accordance with the circular buffering scheme with a frame rate that is twice the source frame rate so as to generate a target video stream having a frame rate which is twice the source frame rate. The frame buffer can be used in a real-time video system, for example in a vehicle.