H04N7/087

Video processing method and video processor

A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.

Video processing method and video processor

A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.

Compressed blanking period transfer over a multimedia link

A transmitting device for communicating via a multimedia communication link includes a compression circuitry that receives blanking period data corresponding to blanking states of video blanking periods. The compression circuitry compresses the blanking period data into compressed blanking period data. The transmitting device also includes an interface that transmits signals corresponding to the compressed blanking period data via one or more multimedia channels of the multimedia communication link.

VIDEO PROCESSING METHOD AND VIDEO PROCESSOR
20220166952 · 2022-05-26 ·

A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.

VIDEO PROCESSING METHOD AND VIDEO PROCESSOR
20220166952 · 2022-05-26 ·

A video processing method and a video processor are provided. The video processing method can be utilized in a video processing system that includes a transmission terminal for generating an input video, the video processor, and a receiving terminal for receiving an output video. The method includes determining whether or not the input video is in at least one of an idle status, an unstable status and a terminated status; switching from outputting the output video to outputting a mute video when the input video is determined to be in at least one of the idle status, the unstable status and the terminated status; inserting a first general control packet for setting mute into one of a plurality of output frames of the mute video; and stopping outputting the mute video after the plurality of output frames of the mute video are outputted.

Image Sensor Bridge Interface
20220132075 · 2022-04-28 ·

An image sensor bridge interface is provided. The interface is situated between an image sensor and a processor. The interface comprises an integrated circuit. The integrated circuit comprises a Field-Programmable Gate Array (FPGA) decoupled from both image signals provided from the image sensor and a processor connected to the integrated circuit. The FPGA separates Ultraviolet (UV) and Infrared (IR) data values from image sensor-provided image data and embeds the UV and IR data values within the horizontal blanking, vertical blanking, and/or active video components of a video feed. The video feed provided from the integrated circuit to the processor using a standard video interface, and the processor providing the video feed or providing UV images, IR images, and Red, Green, and Blue (RGB) images separated from the video feed to a computing core of a host device.

Image Sensor Bridge Interface
20220132075 · 2022-04-28 ·

An image sensor bridge interface is provided. The interface is situated between an image sensor and a processor. The interface comprises an integrated circuit. The integrated circuit comprises a Field-Programmable Gate Array (FPGA) decoupled from both image signals provided from the image sensor and a processor connected to the integrated circuit. The FPGA separates Ultraviolet (UV) and Infrared (IR) data values from image sensor-provided image data and embeds the UV and IR data values within the horizontal blanking, vertical blanking, and/or active video components of a video feed. The video feed provided from the integrated circuit to the processor using a standard video interface, and the processor providing the video feed or providing UV images, IR images, and Red, Green, and Blue (RGB) images separated from the video feed to a computing core of a host device.

Image sensor bridge interface
11570382 · 2023-01-31 · ·

An image sensor bridge interface is provided. The interface is situated between an image sensor and a processor. The interface comprises an integrated circuit. The integrated circuit comprises a Field-Programmable Gate Array (FPGA) decoupled from both image signals provided from the image sensor and a processor connected to the integrated circuit. The FPGA separates Ultraviolet (UV) and Infrared (IR) data values from image sensor-provided image data and embeds the UV and IR data values within the horizontal blanking, vertical blanking, and/or active video components of a video feed. The video feed provided from the integrated circuit to the processor using a standard video interface, and the processor providing the video feed or providing UV images, IR images, and Red, Green, and Blue (RGB) images separated from the video feed to a computing core of a host device.

Image sensor bridge interface
11570382 · 2023-01-31 · ·

An image sensor bridge interface is provided. The interface is situated between an image sensor and a processor. The interface comprises an integrated circuit. The integrated circuit comprises a Field-Programmable Gate Array (FPGA) decoupled from both image signals provided from the image sensor and a processor connected to the integrated circuit. The FPGA separates Ultraviolet (UV) and Infrared (IR) data values from image sensor-provided image data and embeds the UV and IR data values within the horizontal blanking, vertical blanking, and/or active video components of a video feed. The video feed provided from the integrated circuit to the processor using a standard video interface, and the processor providing the video feed or providing UV images, IR images, and Red, Green, and Blue (RGB) images separated from the video feed to a computing core of a host device.

TRANSMISSION SYSTEM AND TRANSMISSION DEVICE
20240333871 · 2024-10-03 · ·

A transmission system including a transmission device capable of transmitting a video signal, and a reception device capable of receiving the video signal transmitted by the transmission device, the transmission system includes: a processor connected to a memory; a video transmission circuit and a video reception circuit that transmit the video signal between the transmission device and the reception device; a transmission-side data transceiving circuit and a reception-side data transceiving circuit that transmit a data signal between the transmission device and the reception device, wherein the processor is configured to selectively execute a video signal transmission mode in which transmission of the video signal is performed and transmission of the data signal superimposed on the video signal is performed, and a data signal transmission exclusive mode in which transmission of the video signal is stopped and transmission of the data signal is performed.