Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

A method may include determining whether the topology of a network includes a direct path between a first endpoint and a second endpoint in the network. A direct path may be used to send a first type of traffic from the first endpoint to the second endpoint whereas any currently available path may be used to send a second type of traffic from the first endpoint to the second endpoint. If the topology of the network does not include a direct path, the first type of traffic may be buffered at the first endpoint until the topology of the network is reconfigured to include the direct path. The topology of the network may be reconfigured when at least one switch in the network reconfigures, for example, by switching from one interconnection to another interconnection pattern. Related systems and articles of manufacture are also provided.

Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

A method may include determining whether the topology of a network includes a direct path between a first endpoint and a second endpoint in the network. A direct path may be used to send a first type of traffic from the first endpoint to the second endpoint whereas any currently available path may be used to send a second type of traffic from the first endpoint to the second endpoint. If the topology of the network does not include a direct path, the first type of traffic may be buffered at the first endpoint until the topology of the network is reconfigured to include the direct path. The topology of the network may be reconfigured when at least one switch in the network reconfigures, for example, by switching from one interconnection to another interconnection pattern. Related systems and articles of manufacture are also provided.

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

A multiway switch, a radio frequency system, and a wireless communication device are provided. The multiway switch is applicable to a wireless communication device being operable in a single-frequency single-transmit mode. The multiway switch includes five T ports and 2.sup.n P ports. The five T ports are configured to be coupled with a radio frequency circuit. The 2.sup.n P ports are configured to be coupled with an antenna system comprising 2.sup.n antennas. The five T ports include one first T port coupled with all of the 2.sup.n P ports. The multiway switch is configured to be coupled with the radio frequency circuit and the antenna system to implement a preset function of the wireless communication device of transmitting a sounding reference signal (SRS) through 2.sup.n antennas corresponding to the 2.sup.n P ports in turn.

A multiway switch, a radio frequency system, and a wireless communication device are provided. The multiway switch includes n T ports and four P ports. At least one of the n T ports is coupled with all of the four P ports, where n is an integer and 4n. The multiway switch is configured to be coupled with a radio frequency circuit and an antenna system of an electronic device to implement a preset function of the electronic device. The antenna system includes four antennas corresponding to the four P ports. The preset function is a function of transmitting a sounding reference signal (SRS) through the four antennas in turn.

A multiway switch, a radio frequency system, and a communication device includes ten T ports and four P ports. The ten T ports include two first T ports, and each of the two first T ports is coupled with all the four P ports. The antenna system includes four antennas corresponding to the four P ports. The multiway switch is coupled with the radio frequency circuit and the antenna system to implement a function of transmitting a sounding reference signal (SRS) through the four antennas in turn.