Embodiments of the present invention provide a model parameter fusion method and apparatus, which relate to the field of machine learning and intend to reduce a data transmission amount and implement dynamical adjustment of computing resources during model parameter fusion. The method includes: dividing, by an i.sup.th node, a model parameter of the i.sup.th node into N blocks, where the i.sup.th node is any node of N nodes that participate in a fusion, and 1≤i≤N≤M; receiving, by the i.sup.th node, i.sup.th model parameter blocks respectively sent by other nodes of the N nodes than the i.sup.th node; fusing, by the i.sup.th node, an i.sup.th model parameter block of the i.sup.th node and the i.sup.th model parameter blocks respectively sent by the other nodes, so as to obtain the i.sup.th general model parameter block; and distributing, by the i.sup.th node, the i.sup.th general model parameter block to the other nodes of the N nodes.

Embodiments of the present invention provide a model, which relate to the field of machine learning and intend to reduce a data transmission amount and implement dynamical adjustment of computing resources during model parameter fusion. The method includes: dividing, by an i.sup.th node, a model parameter of the i.sup.th node into N blocks, where the i.sup.th node is any node of N nodes that participate in a fusion, and 1iNM; receiving, by the i.sup.th node, i.sup.th model parameter blocks respectively sent by other nodes of the N nodes than the i.sup.th node; fusing, by the i.sup.th node, an i.sup.th model parameter block of the i.sup.th node and the i.sup.th model parameter blocks respectively sent by the other nodes, so as to obtain the i.sup.th general model parameter block; and distributing, by the i.sup.th node, the i.sup.th general model parameter block to the other nodes of the N nodes.

The present application discloses a CPU interconnect apparatus and system, and a CPU interconnect control method and control apparatus. The CPU interconnect apparatus includes two gating units and one first intermediate line. Each gating unit includes a first terminal and a second terminal. The first terminal is connected to the second terminal when the gating unit is in a first state. The first terminal is disconnected from the second terminal when the gating unit is in a second state. The two first terminals of the two gating units are connected to two CPUs in a first node. The two second terminals of the two gating units are connected to two ends of the first intermediate line, or the two second terminals of the two gating units are configured to connect to two CPUs in a second node.