A module includes a substrate, a component mounted on a top surface that is one principal surface of the substrate, a first shielding film provided on a top surface and a side surface of the component, a sealing resin provided on the top surface of the substrate and seals the component, and a second shielding film provided on a top surface of the sealing resin. A hole is provided on a top surface of the sealing resin, to reach at least a part of the first shielding film. The second shielding film disposed in the hole is brought into contact with the first shielding film at positions facing a top surface and a side surface of the component.

An assembly comprises a circuit board structure and a plurality of connection portions. The circuit board structure has a main circuit board and a supplemental circuit board. The main circuit board is formed with an accommodating portion. The accommodating portion is recessed downward in an up-down direction from an upper surface of the main circuit board. The main circuit board has a plurality of upper main conductive portions which are formed on the upper surface of the main circuit board. The supplemental circuit board has a plurality of upper supplemental conductive portions which are formed on an upper surface of the supplemental circuit board. The supplemental circuit board is, at least in part, accommodated in the accommodating portion. Each of ones of the connection portions connects a respective one of the upper main conductive portions and a respective one of the upper supplemental conductive portions with each other.

A module substrate for a semiconductor module including a wiring substrate having an upper surface and a lower surface opposite to each other and including a wiring formed therein, the wiring substrate having at least one through groove in at least one sidewall and extending in a thickness direction, and a through-groove test terminal including at least one contact pad, a surface of the contact pad being exposed from an inner wall of the through-groove, the contact pad being spaced apart from a vertical plane extending from the sidewall of the wiring substrate may be provided.

Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors.

A package structure includes a substrate, a sensor, a base, a lead frame, conductive vias and patterned circuit layer. The substrate includes a component-disposing region and electrode contacts. The sensor is disposed at the component-disposing region and electrically connected to the electrode contacts. The base covers the substrate with its bonding surface and includes a receiving cavity, a slanted surface extended between a bottom surface of the receiving cavity and the bonding surface, and electrodes disposed on the bonding surface and electrically connected to the electrode contacts respectively. The sensor is located in the receiving cavity. The lead frame is disposed at the base. The conductive vias penetrates the base and electrically connected to the lead frame. The patterned circuit layer is disposed on the slanted surface and electrically connected to the conductive vias and the electrodes.

A method of manufacturing a component carrier includes (i) forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; (ii) assembling a component to the stack; and (iii) forming a thermally conductive tongue having an embedded portion embedded in the stack and having an exposed portion protruding beyond the stack, where a first width of the tongue in the embedded portion is different from a second width of the tongue in the exposed portion. A corresponding component carrier includes analogous features.

A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.

An angled circuit board connector includes a unitary connector block having first and second board-contacting faces. The first and second board-contacting faces are arranged relative to each other at an operative angle. The connector block includes a block body. The first and second board-contacting faces face outward from the block body. A first connector port is located on the first board-contacting face. A second connector port is located on the second board-contacting face. A connector trace extends through at least a portion of the block body between the first and second board-contacting faces. The connector trace electrically connects the first and second connector ports.

An electronic device module includes: a substrate; at least one electronic device mounted on a first surface of the substrate; a connection portion mounted on the first surface of the substrate; and a shielding portion disposed along an external surface of the connection portion and electrically connected to a ground of the substrate through at least one connection conductor.

A semi-finished product for the production of a printed circuit board having a plurality of alternately arranged insulating layers and conductive layers and at least one hard gold-plated edge connector is characterized by the hard gold-plated edge connector being arranged on an inner conductive layer of the semi-finished product and being fully covered by at least one group of an insulating layer and a conductive layer. The inventive Method for producing a printed circuit board having a plurality of alternately arranged insulating layers and conductive layers and at least one hard gold-plated edge connector, where an outer conductive layer is surface treated, is characterized by the steps of providing a hard gold-plated edge connector on a group of an insulating layer and a conductive layer, covering the conductive layer and the hard gold-plated edge connector with at least one group of an insulating layer and a conductive layer, surface-treating an outer conductive layer to form connector pads for wire bonding of electronic components, cutting the insulating layers and the conductive layers down to the conductive layer forming the hard gold-plated edge connector, removing the insulating layers and conductive layers from the hard gold-plated edge connector. The inventive printed circuit board comprised of a plurality of alternately arranged insulating layers and conductive layers and at least one hard gold-plated edge connector is characterized by the hard gold-plated edge connector being arranged on an inner conductive layer of the printed circuit board, and the inner conductive layer forming the hard gold-plated edge connector protruding from the plurality of insulating layers and conductive layers.