A device source wafer includes a wafer substrate, devices formed on or in the wafer substrate at a location on the wafer substrate, and test structures disposed on the wafer substrate connected to some but not all of the devices. The devices include a first device disposed at a first location and a second device disposed at a second different location on the wafer substrate. The test structures include at least a first test structure connected to the first device and a second test structure connected to the second device. The first test structure is adapted to measuring a characteristic of the first device and the second test structure is adapted to measuring the characteristic of the second device. An estimated characteristic of unmeasured devices is derived from the first and second device locations and measured characteristics and the device is selected based on the estimated characteristic.

An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.

A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

A method for manufacturing a multilayer coil includes preparing a first substrate by forming a first conductor pattern on a first insulating base material layer, preparing a second substrate by forming a second conductor pattern on a second insulating base material layer, and joining a surface of the first substrate on which the first conductor pattern is formed and a surface of the second substrate on which the second conductor pattern is formed together with only a joining layer made of a thermoplastic resin interposed therebetween. Amounts of deformation of the first and second insulating base material layers are less than that of the joining layer at a fusion temperature. The first and second conductor patterns are each a coil pattern having a coil axis that extends in a lamination direction in which the first substrate and the second substrate are laminated together.

A method for forming a pattern on a substrate structure without using a mask layer and a substrate structure are provided. The method includes providing an electrically insulating substrate structure including a thermally conductive and electrically insulating layer, forming at least one electrically conductive recess by removing one part of the electrically conductive layer by a machining process so as to form a predetermined thickness ratio between a thickness of the electrically conductive recess and a thickness of the electrically conductive layer, and removing another part of the electrically conductive layer that is reserved below the electrically conductive recess so that the electrically conductive recess forms an electrically conductive groove.

A wiring body includes an adhesive :layer and a conductor pattern bonded to the adhesive layer. A surface roughness of an adhesive surface in the conductor pattern bonded to the adhesive layer is rougher than a surface roughness of another surface, which is a surface of the conductor pattern except for the adhesive surface in the conductor pattern.

A wiring body includes a conductive portion that includes a contact surface having a concave-convex shape, and an adhesive layer stacked on the contact surface. The conductive portion further includes a top surface facing the contact surface that contains conductive particles. The adhesive layer includes a smooth portion with a smooth main surface provided at a constant thickness, and a protrusion that protrudes from the main surface toward a side of the conductive portion provided on the smooth portion to correspond to the conductive portion. The protrusion comes into contact with the contact surface and includes a concave-convex surface complementary to the concave-convex shape of the contact surface. The contact surface is positioned on a side of the top surface with respect to the main surface and a unit length of the contact surface is larger than a unit length of the top surface.

The present invention relates to a method of manufacturing a circuit board, which includes the steps of preparing an insulating substrate (A), fowling a polymer layer (B) containing a water-soluble polymer on at least one surface of the insulating substrate, forming a groove (C) in the polymer layer (B), forming a circuit pattern (E) in the groove (C) with use of a conductive material (D), and removing the polymer layer (B) with use of an aqueous solvent (F).

A laminate for printed wiring board is used in a method of manufacturing printed wiring boards that includes a process of forming a circuit by any one of a semi-additive method, a partly additive method, a modified semi-additive method, and an embedding method. The laminate includes an insulating resin substrate, a metal layer 1 and a metal layer 2 in this order. When a cross section that is parallel to the thickness direction of the laminate is processed by means of ion milling and the cross sections of the metal layer 1 and the metal layer 2 were observed with EBSD, each of the metal layer 1 and the metal layer 2 has one or plural crystal grain(s) at the processed cross section, and an area ratio of the total area of crystal grains of which a difference in angle of the <100> crystal direction from a perpendicular of the processed cross section is 15° or less from among the one or plural crystal grains to the total area of the plural crystal grains was 15% or higher but less than 97% in the metal layer 1 and the metal layer 2.

A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.