A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

A multi-layer circuit board, successively constituted by surface sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, surface sticking layer, said multi-layer circuit board is provided with a hole, a hole wall of said hole is formed with conductive seed layer, and partial outer surface of said surface sticking layer is formed with a circuit pattern layer of conductive seed layer, wherein said conductive seed layer comprises a ion implantation layer implanting below the hole wall of said hole and below partial outer surface of said surface sticking layer.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.