Depicted embodiments are directed to an Application Specific Electronics Packaging (“ASEP”) system, which enables the manufacture of additional products using reel to reel (68a, 68b) manufacturing processes as opposed to the “batch” processes used to currently manufacture electronic products and MIDs. Through certain ASEP embodiments, it is possible to integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memory, impedance control, and multi-layer functionality directly into a product.

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.

A method for forming a metal film includes forming an oxide layer on a to-be-treated surface of a to-be-treated object by bringing the to-be-treated surface into contact with a reaction solution containing fluorine and an oxide precursor, removing fluorine in the oxide layer, supporting a catalyst on the oxide layer by bringing the oxide layer into contact with a catalyst solution, and depositing a metal film on the oxide layer by bringing the oxide layer into contact with an electroless plating liquid.

A coating agent for forming an oxide film; a method for producing an oxide film; and a method for producing a metal-plated structure, where the stability of the coating agent can be enhanced, and an oxide film which can be plated and has high adhesion to a substrate can be easily formed. The coating agent for forming an oxide film is a liquid coating agent, essentially contains titanium atoms, and optionally contains silicon atoms and copper atoms, wherein the ratio of the sum of the titanium atoms and copper atoms to the silicon atoms is 1:0-3:2. The method for producing an oxide film includes applying the coating agent to a substrate and heating to form an oxide film. The method for producing a metal-plated structure includes: a metal-film-forming step for forming a metal film on the oxide film; and a baking step for baking the metal film.

Provided is a surface-treated copper foil excellent in laser processability. The surface-treated copper foil includes a roughened surface formed by subjecting a surface to a roughening treatment, in which when measured using a three-dimensional roughness meter, the roughened surface has a surface skewness Ssk within a range of from −0.300 to less than 0 and an arithmetic mean summit curvature Ssc within a range of from 0.0220 nm.sup.−1 to less than 0.0300 nm.sup.−1.

Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.

A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.

A method for manufacturing a printed wiring board includes forming the outermost conductor layer on the outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, and forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in a range of 0.22 μm to 0.38 μm.

A molded interconnect device that comprises a substrate and conductive elements disposed on the substrate is provided. The substrate comprising a polymer composition containing a polymer matrix that includes a thermotropic liquid crystalline polymer and from about 10 parts to about 80 parts by weight of a mineral filler per 100 parts by weight of the polymer matrix. The mineral filler has an average diameter of about 25 micrometers or less. The polymer composition contains copper in an amount of about 1,000 parts per million or less and chromium in an amount of about 2,000 parts per million or less, and further exhibits a surface resistivity of about 1×1014 ohm or more.