The present invention relates to a method for reducing the optical reflectivity of a copper and copper alloy circuitry wherein a thin palladium or palladium alloy layer is deposited by immersion-type plating onto said copper or copper alloy. Thereby, a dull greyish or greyish black or black layer is obtained and the optical reflectivity of said copper or copper alloy circuitry is reduced. The method according to the present invention is particularly suitable in the manufacture of image display devices, touch screen devices and related electronic components.

A light source includes a side-emitting, light emitting diode (LED) that is mounted on a printed circuit board (PCB) or other substrate. The LED is used to illuminate a target such as a sensor or the like. In order to increase the amount of illumination emitted by the LED that reaches the target, a reflector is located on the PCB. The reflector receives light that is emitted by the LED and directed toward the PCB and not the target. This light, which would otherwise be lost, is reflected by the reflector and re-directed toward the target. By reducing the amount of light is lost, the amount of light reaching the target can be increased without a commensurate increase in the current supplied to the LED.

Provided is a method of manufacturing a metal wiring on a substrate, including the steps of: forming a first layer containing a first material in at least part on the substrate; forming a crack in the first layer to form the first layer having the crack; and forming a second layer containing a second material in the first layer having the crack.

A method for manufacturing an antenna includes the steps of: providing a ferrite sheet; forming a via hole through the ferrite sheet, wherein the via hole is connected between a first surface and a second surface of the ferrite sheet; forming a nonconductive ink layer on the first surface and the second surface and in the via hole of the ferrite sheet; applying a displacement process to the nonconductive ink layer so as to form a first metal layer on the nonconductive ink layer; and applying a thickening process to the first metal layer so as to form a second metal layer on the first metal layer, wherein the first metal layer and the second metal layer both extend from the first surface through the via hole to the second surface of the ferrite sheet.

Adhesion of an underlying diffusion barrier metal film and an electroless copper plating film with respect to an insulating film can be improved. A method for manufacturing a wiring structure includes a process of forming the underlying diffusion barrier metal film 5, including a base metal with respect to copper, on the insulating film 1; and a process of forming the electroless copper plating film 6 on the underlying diffusion barrier metal film 5 by performing an electroless copper displacement plating process with a copper displacement plating solution. The copper displacement plating solution is an acidic copper displacement plating solution of pH1 to pH4, in which copper ions are contained but a reducing agent for reducing the copper ions is not contained.

A printed circuit board includes, an insulating substrate, a metal conductor which is formed on the insulating substrate, a solder resist coating a part of the metal conductor, a scooped-out portion of the metal conductor formed in the vicinity of an end of the solder resist, and a metal layer coating the scooped-out portion.

Light emitting devices and substrates are provided with improved plating. In one embodiment, a light emitting device can include a submount and one or more light emitting diodes (LED) chips disposed over the submount. In one embodiment, the submount can include a copper (Cu) substrate, a first metallic layer of material that is highly reflective disposed over the Cu substrate for increased brightness of the device, and a second metallic layer disposed between the Cu substrate and the first metallic layer for forming a barrier therebetween.

A component carrier and a method of manufacturing the component carrier are disclosed. The component carrier includes i) a first exposed conductor area with a first protective layer structure on a first electrically conductive layer structure; and ii) a second exposed conductor area with a second protective layer structure on a second electrically conductive layer structure. The first protective layer structure and the second protective layer structure include a common non-exposed layer structure; and different exposed layer structures.

A wiring board includes an insulation resin layer, and a wiring conductor positioned on the insulation resin layer. The wiring conductor includes a first and second underlying metal layers, a wiring metal layer positioned on the second underlying metal layer, a tin layer positioned covering the first underlying metal layer, the second underlying metal layer, and the wiring metal layer, and a silane coupling agent layer positioned covering the tin layer. When the wiring conductor is seen in a cross section in a width direction, the wiring metal layer includes, from the first underlying metal layer side, a portion with a width narrower than a width of the first underlying metal layer, a portion with a width equal to the width of the first underlying metal layer, and a portion with a width wider than the width of the first underlying metal layer.