A ceramic circuit substrate having high bonding performance and excellent thermal cycling resistance properties, having a circuit pattern provided on a ceramic substrate with a braze material layer interposed therebetween, and a protruding portion formed by the braze material layer protruding from the outer edge of the circuit pattern, wherein: the braze material layer includes Ag, Cu, Ti, and Sn or In; and an Ag-rich phase is formed continuously for 300 μm or more, towards the inside, from an outer edge of the protruding portion, along a bonding interface between the ceramic substrate and the circuit pattern, and has a bonding void ratio of 1.0% or less.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A fluororesin base material containing a fluororesin as a main component includes a modified layer on at least a partial region of a surface thereof, the modified layer containing a siloxane bond and a hydrophilic organofunctional group, and a surface of the modified layer having a contact angle of 90° or less with pure water.

A multi-layer circuit board, successively constituted by surface sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, surface sticking layer, said multi-layer circuit board is provided with a hole, a hole wall of said hole is formed with conductive seed layer, and partial outer surface of said surface sticking layer is formed with a circuit pattern layer of conductive seed layer, wherein said conductive seed layer comprises a ion implantation layer implanting below the hole wall of said hole and below partial outer surface of said surface sticking layer.

The present inventive concept relates to an unfoldable layered connection comprising: a substrate; a node of connector material arranged to contact the substrate; a first extension comprising a core of connector material arranged to be in contact with the node, and flexible material arranged to at least partially enclose the core; a second extension comprising a core of connector material arranged to be in contact with the first extension via a second node of connector material, wherein the first extension is configured to be hingedly connected to the node, thereby allowing unfolding of the first extension along a z-axis being perpendicular to an extension plane of a major surface of the substrate; and wherein the second extension is hingedly connected to the second node, thereby allowing unfolding of the second extension along the z-axis, and wherein the second node is moveable along the z-axis via unfolding of the first extension.

The present inventive concept relates to a foldable layered connection comprising: a substrate having a first major surface and an opposing second major surface; a node of connector material arranged to contact the substrate via the first major surface; a released extension comprising a core of connector material arranged to be in communicative contact with the node of connector material, and flexible material arranged to at least partially enclose the core; wherein the released extension is configured to be hingedly connected to the node and to fold towards the second major surface, and wherein a portion of the core of connector material is exposed, forming a contact of connector material, wherein the contact is electrically isolated from the second major surface and arranged such that it is facing away from the second major surface when the released extension is folded towards the second major surface.

A direct patterning method of touch panel is provided. A substrate having a display region and a peripheral region is provided. A periphery circuit having a bonding pad is disposed on the periphery region. A metal nanowire layer made of metal nanowires are disposed on the display region and the peripheral region. A photosensitive pre-cured layer is disposed on the metal nanowire layer. A photolithography process is performed, which includes exposing the pre-cured layer to define a removal area and a reserved area, and removing the pre-cured layer and the metal nanowire layer on the removal area using a developer solution to form a touch-sensing electrode disposed on the display region and to expose the bonding pad disposed on the periphery region. The touch sensing electrode made of the pre-cured layer and the metal nanowire layer is electrically connected to the periphery circuit.

A method for treating a substrate having millimeter and/or micrometer and/or nanometer structures. The method includes applying at least one protective material to the structures, wherein the at least one protective material can be dissolved in a solvent, and the structures are produced by an imprinting process.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Methods of making metal patterns on flexible substrates are provided. Releasable solid layer is selectively formed on a patterned surface of the flexible substrate by applying a liquid solution thereon. Metal patterns on the flexible substrate can be formed by removing the releasable solid layer after metallization. In some cases, the releasable solid layer can be transferred from the patterned surface to a transfer layer where the metal patterns are formed.