There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

A semiconductor memory device includes a substrate, first conductor layers, second conductor layers, a third conductor layer, and an insulator layer. The substrate includes a first region, a second region, and a third region separating the first and second regions. The first conductor layers are above the first region. The second conductor layers are above an uppermost one of the first conductor layers. The third conductor layer is above the second region. The insulator layer is above the second and third regions. The insulator layer includes first and second portions. The first portion is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a substrate surface direction. The second portion extends along a substrate thickness direction and contacts a surface of the substrate in the third region.

The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.

A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.

A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.

A semiconductor memory device includes a substrate, first conductor layers, second conductor layers, a third conductor layer, and an insulator layer. The substrate includes a first region, a second region, and a third region separating the first and second regions. The first conductor layers are above the first region. The second conductor layers are above an uppermost one of the first conductor layers. The third conductor layer is above the second region. The insulator layer is above the second and third regions. The insulator layer includes first and second portions. The first portion is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a substrate surface direction. The second portion extends along a substrate thickness direction and contacts a surface of the substrate in the third region.

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.