A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

The present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) region and a method for forming the semiconductor device structure. The semiconductor device structure also includes a well region disposed in a semiconductor substrate, a first shallow trench isolation (STI) structure extending into the well region. The first STI structure comprises a first liner contacting the well region; a second liner covering the first liner and contacting the pad oxide layer and the pad nitride layer; a third liner covering the second liner, wherein the first liner, the second liner and the third liner are made of different materials; and a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate, where a plurality of contact pads are formed on the substrate; depositing a dielectric layer on the substrate, where the dielectric layer fills gaps between the contact pads and covers the contact pads; and etching the dielectric layer through a plasma etching process to expose the contact pads, where an etching gas used in the plasma etching process includes an oxygen-free etching gas. The manufacturing method can avoid the formation of metal oxides on the contact pads, and avoid residual conductive metal particles or metal compounds on surfaces of the contact pads and the adjacent dielectric layers, which is beneficial to ensure the electrical performance of the semiconductor structure, thereby improving the use reliability of the semiconductor structure.

The disclosure relates to a semiconductor storage device and a forming method thereof. The semiconductor storage device includes a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surround the plurality of active region structures; a plurality of conductive line structures, extending parallel to each other along a first direction, the conductive line structure include a first region and a second region, the first region being located over each of the plurality of active region structures, the second region is located over the shallow trench isolation structure; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.

An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10.sup.−4 Ωcm to 1.0×10.sup.4 Ωcm or a sheet resistance in a range from 1.0×10.sup.2Ω/□ to 1.0×10.sup.10Ω/□.

A non-conformal, highly selective liner for etch methods in semiconductor devices is described. A method comprises forming a film stack on a substrate; etching the film stack to form an opening; depositing a non-conformal liner in the opening; etching the non-conformal liner from the bottom of the opening; and selectively etching the film stack relative to the non-conformal liner to form a logic or memory hole. The non-conformal liner comprises one or more of boron, carbon, or nitrogen.

A semiconductor die includes semiconductor substrate and interconnection structure. Interconnection structure includes first conductive lines, first conductive patterns, first pillar stacks, second pillar stacks, gate patterns. First conductive lines extend parallel to each other in first direction and are embedded in interlayer dielectric layer. First conductive patterns are disposed in row along first direction and are embedded in interlayer dielectric layer beside first conductive lines. First pillar stacks include first pairs of metallic blocks separated by first dielectric material blocks. Second pillar stacks include second pairs of metallic blocks separated by second dielectric material blocks. Each second pillar stack is electrically connected to respective first conductive pattern. Gate patterns extend substantially perpendicular to first conductive lines. Each gate pattern directly contacts one respective second pillar stack and extends over a group of first pillar stacks.