The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.

Embodiments provide a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a substrate including a plurality of semiconductor layers arranged at intervals and an isolation layer positioned between adjacent two of the plurality of semiconductor layers, a given one of the plurality of semiconductor layers and the isolation layer being internally provided with trenches, and each of the trenches including a first region, a second region and a third region sequentially distributed; forming a sacrificial layer on an inner wall of the trench in the first region and the second region; forming an insulating layer filling up the trench on a surface of the sacrificial layer; removing the sacrificial layer in the second region, and removing the isolation layer of a first thickness to form voids surrounding the given semiconductor layer.

In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.

Disclosed herein is an apparatus that includes a plurality of cell capacitors arranged in a memory cell array region of a semiconductor substrate, each of the plurality of cell capacitors having a first electrode, a second electrode and an insulating film therebetween to electrically disconnect the first and second electrodes, a first conductive member including the plurality of cell capacitors therein, the first conductive member being electrically connected in common to the first electrodes of the plurality of cell capacitors, and a second conductive member formed on an upper surface of the first conductive member, a material of the second conductive member being different from that of the first conductive member. A side surface of the first conductive member is free from the second conductive member.

A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al.sub.2O.sub.3 film between the top electrode and the dielectric film, wherein the doped Al.sub.2O.sub.3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al.sub.2O.sub.3.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

A semiconductor device includes a substrate, a pair of source/drain regions, a metal-containing layer, and a gate structure. The substrate includes a trench. The source/drain regions are disposed in the substrate on opposite sides of the trench. The metal-containing layer is disposed under the trench, wherein the metal-containing layer includes a metal silicide layer, and the metal-containing layer and the substrate on opposite sidewalls of the trench collectively form the channel region of the semiconductor device. The gate structure is disposed in the trench. The gate structure includes a gate dielectric layer disposed on opposite sidewalls of the trench, a buffer layer disposed on the metal-containing layer, and a gate conductive layer disposed on the buffer layer and filling in the trench.

Embodiments relate to a semiconductor structure and a method for fabricating. The semiconductor structure includes: a substrate, word lines, bit lines, and word line isolation structures. Active pillars arranged in an array are provided on a surface of the substrate, and the active pillars include channel regions, and a top doped region positioned on an upper side of the channel region and a bottom doped region positioned on a lower side of the channel region. The word lines extend along a first direction and surround the channel regions of a row of the active pillars arranged along the first direction. The bit lines extend along a second direction and are electrically connected to the bottom doped regions of a column of the active pillars arranged along the second direction, and in a direction facing away from the surface of the substrate.