A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; during the write operation after the page erase operation, the positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line; and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.

Material layers including first and second poly-Si layer are formed on a P-layer substrate. Holes which are parallel to each other and each of which is continuous in a first direction are formed in the material layers. The first and second poly-Si layers are each divided by the holes in a second direction orthogonal to the first direction in plan view. Gate insulating layers and P-layer Si pillars are formed in the holes. The P-layer Si pillars are isolated from one another by the gate insulating layers. A dynamic flash memory is formed in which a first gate conductor layer is connected to a plate line, a second gate conductor layer is connected to a word line, the P-layer Si pillars serve as channels, and one of the N.sup.+ layers below and above the P-layer Si pillars is connected to a source line.

A memory device includes pages containing memory cells arranged in an array on a substrate. In each memory cell, a voltage applied to a first gate conductor layer, second gate conductor layer, third gate conductor layer, first impurity layer, and second impurity layer is controlled to form a hole group by impact ionization inside a channel semiconductor layer, and a page write operation of holding the hole group and a page erase operation of removing the hole group are performed. The first impurity layer is connected to a source line, the second impurity layer to a bit line, the first gate conductor layer to a first plate line, the second gate conductor layer to a second plate line, and the third gate conductor layer to a word line. A page erase operation is performed without inputting a positive or negative bias pulse to the bit line and the source line.

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

Embodiments of the disclosure provide a semiconductor structure, a method for manufacturing the same and a memory. The semiconductor structure includes a plurality of active pillars and a plurality of conductor lines. Each of the conductor lines includes a plurality of metal layers located in a gap between two adjacent active pillars and a metal compound layer partially surrounding the plurality of active pillars.

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple semiconductor pillars, memory structures, and multiple transistors. The multiple semiconductor pillars are arrayed along a first direction and a second direction. Each semiconductor pillar includes a first portion and a second portion on the first portion. The memory structure includes a first electrode layer, a dielectric layer and a second electrode layer. The first electrode layers cover sidewalls of the first portions and are located in first filling regions arranged at intervals. Each first filling region surrounds a sidewall of the first portion. The dielectric layers cover at least surfaces of the first electrode layers. The second electrode layers cover surfaces of the dielectric layers. Channel structures of the transistors are located in the second portions, and extend in a same direction as the second portions.

A stacked memory device includes a plurality of lower word lines extending in a first direction, a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction, and a plurality of upper word lines positioned over the bit line and extending in the first direction. The stacked memory device also includes a plurality of lower memory cells including a lower capacitor and a lower switching element between the lower word lines and the bit line. The stacked memory device further includes a plurality of upper memory cells including an upper capacitor and an upper switching element between the bit line and the upper word lines.

Disclosed in the embodiments of the present disclosure are a semiconductor structure and method for manufacturing same, and a memory. The semiconductor structure includes: a plurality of first active columns arranged in an array along a first direction and a second direction, a plurality of first electrodes located in first grooves arranged at intervals, a plurality of first dielectric layers, and a second electrode covering surfaces of the first dielectric layers. The first direction and the second direction are perpendicular to the extension direction of the first active column, and the first direction is intersected with the second direction. Each first electrode covers a side wall of one of the first active columns. Each first groove surrounds a surface of each first active column. Each first dielectric layer covers the side wall of one of the first electrodes and a bottom of a gap between two adjacent first electrodes.

A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.