A semiconductor device includes a semiconductor substrate, a word line trench and a word line structure. The word line trench includes a first word line trench and a second word line trench. The word line structure includes a first word line structure part and a second word line structure part connected to each other. The first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench; and the first word line structure part includes an avoidance region, and the top surface of the avoidance region is aligned with the top surface of the second word line structure part, and the avoidance region is provided with insulating material.

Embodiments provide a memory device and a method for fabricating the same, relating to the field of semiconductor technology. The method includes: forming buried gate structures in a first direction in a substrate; patterning the substrate, cutting off the buried gate structures, and forming active structures arranged at parallel intervals and isolation grooves between the active structures in a second direction, where the active structures are island-shaped columnar bodies, and the active structures include the buried gate structures; forming isolation structures in the isolation grooves, where surfaces of the isolation structures are flush with surfaces of the active structures; and forming conductive word lines in the first direction on the surfaces of isolation structures and the surfaces of the active structures, where the conductive word lines cover upper surfaces of the buried gate structures in the active structures.

The invention provides a semiconductor structure and a fabrication method for same. The semiconductor structure comprises: a substrate; a plurality of word-line structures extending along a first direction on the substrate and arranged at intervals along a second direction, wherein the second direction is perpendicular to the first direction; a plurality of spacer structures disposed above the plurality of word-line structures, wherein at least one of the plurality of spacer structures comprises a first spacer layer and an air gap, the first spacer layer is disposed at a bottom portion of the spacer structures, the air gap is disposed on the first spacer layer, and the air gap is located between the plurality of first spacer layers along the second direction; and a plurality of contact plugs disposed between the plurality of spacer structures.

Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals and an isolation structure located between the active regions; a word line (WL) trench, penetrating through the active region and the isolation structure along a first direction; and a WL, located in the WL trench, wherein on a section in a second direction, a first height difference is formed between the active region and the isolation structure; and the second direction is parallel to the substrate and perpendicular to the first direction.

The present disclosure provides a semiconductor device, a method of manufacturing a semiconductor device and an electronic device. The method of manufacturing a semiconductor device includes: forming word line trenches on a semiconductor substrate, forming a word line structure in each of the word line trenches, and finally forming active regions. The word line trenches pass through the semiconductor substrate without passing through other material.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, wherein the base includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed in the base, and the word line trench exposes a part of the active region and the shallow trench isolation structure; forming a first intermediate structure in the word line trenches, wherein the first intermediate structure covers side walls and a bottom wall of the word line trench, a first trench is formed in the first intermediate structure, the first intermediate structure includes a sacrificial structure, and the sacrificial structure includes a horizontal portion; and removing the horizontal portion of the sacrificial structure, and closing the first trench, and forming an air chamber.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate, where a plurality of contact pads are formed on the substrate; depositing a dielectric layer on the substrate, where the dielectric layer fills gaps between the contact pads and covers the contact pads; and etching the dielectric layer through a plasma etching process to expose the contact pads, where an etching gas used in the plasma etching process includes an oxygen-free etching gas. The manufacturing method can avoid the formation of metal oxides on the contact pads, and avoid residual conductive metal particles or metal compounds on surfaces of the contact pads and the adjacent dielectric layers, which is beneficial to ensure the electrical performance of the semiconductor structure, thereby improving the use reliability of the semiconductor structure.

A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.

The disclosure relates to a semiconductor storage device and a forming method thereof. The semiconductor storage device includes a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surround the plurality of active region structures; a plurality of conductive line structures, extending parallel to each other along a first direction, the conductive line structure include a first region and a second region, the first region being located over each of the plurality of active region structures, the second region is located over the shallow trench isolation structure; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.