A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

A method of forming a plug for a semiconductor device and a semiconductor device thereof are disclosed. The proposed method of forming a plug for a semiconductor device, wherein the semiconductor device includes a deep trench (DT) structure and a storage node configured in the DT structure, comprising: (a) filling a single film in the DT structure and to cover the storage node; and (b) etching back the single film to form the plug located in the DT structure and around the storage node, wherein the single film forms a liner of a single type.

The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; disposing a semiconductive material over the semiconductor substrate and conformal to the fin portion; disposing a conductive material over the semiconductive material; disposing an insulating material over the conductive material; disposing a patterned photoresist over the insulating material; applying an electric field at a first predetermined angle toward a plasma to remove a portion of the insulating material exposed through the patterned photoresist to form an insulating layer, to remove a portion of the conductive material under the portion of the insulating material to form a conductive layer, and to remove a portion of the semiconductive material under the portion of the insulating material to form a semiconductive layer; and removing the patterned photoresist from the insulating layer.

The present application provides a memory device having a memory cell with reduced protrusion protruding from the memory cell. The memory device includes a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; a semiconductive layer disposed conformal to the fin portion; a conductive layer disposed over the semiconductive layer; an insulating layer disposed over the conductive layer; and a protrusion including a first protruding portion laterally protruding from the semiconductive layer and along the surface, a second protruding portion laterally protruding from the conductive layer and over the first protruding portion, and a third protruding portion laterally protruding from the insulating layer and over the second protruding portion, wherein the protrusion has an undercut profile.

A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10.sup.−4 Ωcm to 1.0×10.sup.4 Ωcm or a sheet resistance in a range from 1.0×10.sup.2Ω/□ to 1.0×10.sup.10Ω/□.

The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows. The transistors on one side of each first isolation stripe and the transistors on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the transistors along the corresponding column. Each capacitor corresponds to one of the transistors and connects the source region of the corresponding transistor.

A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate and bit line structures on the substrate; forming a first isolation layer, the first isolation layer being located on side walls of the bit line structures and on the substrate; forming a second isolation layer, the second isolation layer covering the first isolation layer located on the side walls of the bit line structures, and exposing the first isolation layer located on the substrate; removing the first isolation layer exposed by the second isolation layer and part of the first isolation layer below the second isolation layer, so that remaining of the first isolation layer is recessed compared to the second isolation layer toward the side walls of the bit line structures to form a groove.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.