Embodiments of the present application relate to the field of semiconductors, and provide a word line driver array and a memory. The word line driver array at least includes: a first transistor, a third transistor, a zeroth transistor and a second transistor arranged sequentially, as well as a zeroth word line, a first word line, a second word line and a third word line parallel to each other, wherein the zeroth word line is connected to a drain of the zeroth transistor, the first word line is connected to a drain of the first transistor, the second word line is connected to a drain of the second transistor, and the third word line is connected to a drain of the third transistor.

A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

A semiconductor device is provided. The device comprises first semiconductor wafer comprising first BEOL structure disposed on first side of first substrate, the first BEOL structure comprising first metallization layer disposed over the first substrate, second metallization layer disposed over the first metallization layer, first storage device disposed between the first and second metallization layers, and first transistor contacting the first storage device, and a first bonding layer disposed over the first BEOL structure. The device also comprises second semiconductor wafer comprising second BEOL structure disposed on first side of second substrate, the second BEOL structure comprising third metallization layer disposed over the second substrate, fourth metallization layer disposed over the third metallization layer, second storage device disposed between the third and fourth metallization layers, and second transistor contacting the second storage device, and second bonding layer disposed over the second BEOL structure and contacting the first bonding layer.

A apparatus includes a memory cell region; a peripheral region adjacent to the memory cell region; first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively; wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.

In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.

Material layers including first and second poly-Si layer are formed on a P-layer substrate. Holes which are parallel to each other and each of which is continuous in a first direction are formed in the material layers. The first and second poly-Si layers are each divided by the holes in a second direction orthogonal to the first direction in plan view. Gate insulating layers and P-layer Si pillars are formed in the holes. The P-layer Si pillars are isolated from one another by the gate insulating layers. A dynamic flash memory is formed in which a first gate conductor layer is connected to a plate line, a second gate conductor layer is connected to a word line, the P-layer Si pillars serve as channels, and one of the N.sup.+ layers below and above the P-layer Si pillars is connected to a source line.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

A semiconductor device includes a first layer including a plurality of wirings arranged in line and space layout and a second layer including a pad electrically connected to at least one of the wirings, wherein the wirings and the pads are patterned by different lithographic processes.

A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.