A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.

Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.

A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A channel hole is formed in a stack including alternating first layers and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are sequentially formed in the channel hole. Laser annealing is performed on the channel layer using laser light. An incidence angle of the laser light on an upper surface of the channel layer causes a total internal reflection to occur at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer that is adjacent to the channel layer.

Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A channel hole is formed in a stack including alternating first layers and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are sequentially formed in the channel hole. Laser annealing is performed on the channel layer using laser light. An incidence angle of the laser light on an upper surface of the channel layer causes a total internal reflection to occur at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer that is adjacent to the channel layer.

A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.