A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one and includes a stepped portion in which, a first pillar disposed in the stepped portion, the first pillar extending in a stacking direction of the stacked body; and a second pillar extending in the stacking direction within the stacked body, the second pillar forming a memory cell at each intersection with at least a part of the plurality of first conductive layers. The first pillar has a semiconductor layer or a second conductive layer extending in the stacking direction and serving as a core material of the first pillar, and a second insulating layer covering a side wall of the semiconductor layer or the second conductive layer and serving as a liner layer of the first pillar.

A semiconductor storage device according to an embodiment includes a substrate, an interconnection layer region, a multi-layered body, a semiconductor body, and a columnar part. The multi-layered body has an end portion facing the interconnection layer region as an end portion in the first direction. The columnar part includes a first portion and a second portion, the first portion is at the end portion of the multi-layered body, the second portion is closer to the substrate than the first portion is. The first portion has a center. The second portion has a center. The center of the second portion in a second direction is displaced in the second direction with respect to the center of the first portion in the second direction. The second direction crosses the first direction.

To provide a highly reliable memory device. A first insulator is formed over a substrate; a second insulator is formed over the first insulator; a third insulator is formed over the second insulator; an opening penetrating the first insulator, the second insulator, and the third insulator is formed; a fourth insulator is formed on the inner side of a side surface of the first insulator, a side surface of the second insulator, and a side surface of the third insulator, in the opening; an oxide semiconductor is formed on the inner side of the fourth insulator; the second insulator is removed; and a conductor is formed between the first insulator and the third insulator; and the fourth insulator is formed by performing, a plurality of times, a cycle including a first step of supplying a gas containing silicon and an oxidizing gas into a chamber where the substrate is placed, a second step of stopping the supply of the gas containing silicon into the chamber; and a third step of generating plasma containing the oxidizing gas in the chamber.

A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. The conductor tier is directly above a lower tier that comprises conductive lines that are horizontally elongated. An insulator tier is vertically between the conductor tier and the lower tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to the conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually directly electrically couple to one of the conductive lines. Insulator walls are in the TAV region. The insulator walls extend vertically through the conductor tier and the insulator tier to the lower tier and are horizontally elongated. Methods are also disclosed.

A semiconductor memory device includes a first insulating layer, a first conductive layer, a first pillar, a second pillar, and a second insulating layer. The first conductive layer contains tungsten. The first conductive layer includes a first sub conductive layer and a second sub conductive layer. The first pillar and the second pillar pass through the first insulating layer and the first conductive layer. The second insulating layer divides the first insulating layer and the first conductive layer. The first sub conductive layer is in contact with the second sub conductive layer and is provided between the second sub conductive layer and the first insulating layer. A fluorine concentration in the first sub conductive layer is lower than that in the second sub conductive layer.

Semiconductor devices may include a first stack structure including interlayer insulating layers and gate electrodes alternately stacked in a first direction perpendicular to an upper surface of a substrate on a first region of the substrate and including a first lower stack structure and a first upper stack structure, a second stack structure including the interlayer insulating layers and sacrificial insulating layers alternately stacked in the first direction on a second region of the substrate and including a second lower stack structure and a second upper stack structure, a channel structure penetrating the first upper stack structure and the first lower stack structure, extending in the first direction, and including a channel layer, and an align key structure penetrating the second lower stack structure and extending in the first direction. The second upper stack structure may include a first align key region on the align key structure.

A semiconductor device includes a semiconductor structure that includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction, extend at different lengths in a second direction on the second region, and include pad regions, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, contact plugs penetrating the pad regions and extending in the first direction on the second region, and contact insulating layers between the gate electrodes and between ones of the contact plugs below the pad regions. The pad regions and the contact insulating layers protrude from the interlayer insulating layers toward the contact plugs in a horizontal direction.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.