A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (In.sub.xSn.sub.yTi.sub.zM.sub.mO.sub.n). In formula 1, 0<x<1, 0≤y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.