A semiconductor storage device includes a field-effect transistor, an interlayer insulation film, a source contact, an opening, and a capacitor. The field-effect transistor is provided on a semiconductor substrate. The interlayer insulation film is provided on the semiconductor substrate. The source contact runs through the interlayer insulation film and is electrically coupled to a source of the field-effect transistor. The opening is provided in a region of the interlayer insulation film including the source contact and allows the source contact to project therein. The capacitor includes a lower electrode, a ferroelectric film, and an upper electrode. The lower electrode is provided along an inside shape of the opening. The ferroelectric film is provided on the lower electrode. The upper electrode is provided on the ferroelectric film to fill the opening.

In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

A semiconductor device includes a first memory cell that includes: a first conductor structure extending along a first lateral direction; a first portion of a first memory film wrapping around a first portion of the first conductor structure; a first semiconductor film wrapping around the first portion of the first memory film; a second conductor structure extending along a vertical direction and coupled to a first sidewall of the first semiconductor film, wherein the first sidewall faces toward or away from a second lateral direction perpendicular to the first lateral direction; and a third conductor structure extending along the vertical direction and coupled to a second sidewall of the first semiconductor film, wherein the second sidewall faces toward or away from the second lateral direction.

A semiconductor device and a method of manufacturing the semiconductor includes a first source layer spaced apart from a substrate and disposed in a memory cell region of the substrate, a second source layer spaced apart from the substrate and disposed in a contact region of the substrate, a cell stacked structure including interlayer insulating layers and conductive patterns alternately stacked on each other over the first source layer, a discharge contact passing through at least a part of the second source layer, and a dielectric layer disposed between the second source layer and the discharge contact.

A semiconductor device and a method of manufacturing the semiconductor includes a first source layer spaced apart from a substrate and disposed in a memory cell region of the substrate, a second source layer spaced apart from the substrate and disposed in a contact region of the substrate, a cell stacked structure including interlayer insulating layers and conductive patterns alternately stacked on each other over the first source layer, a discharge contact passing through at least a part of the second source layer, and a dielectric layer disposed between the second source layer and the discharge contact.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

A stacked structure includes a ferroelectric layer, and a tunnel barrier layer joined to the ferroelectric layer. The main component of the ferroelectric layer is aluminum nitride, and the main component of the tunnel barrier layer is magnesium oxide.