Disclosed are a 3D non-volatile memory, an operating method thereof, and a manufacturing method thereof. The 3D non-volatile memory includes a bit line formed to extend in a vertical direction and horizontal structures contacting the bit line while being formed to extend in a horizontal direction and being space in the vertical direction. Each of the horizontal structures includes a ferroelectric layer contacting the bit line, a middle metal layer surrounded by the ferroelectric layer, a dielectric layer surrounded by the middle metal layer, and a word line surrounded by the dielectric layer.

A semiconductor device includes a first concentric structure extending along a vertical direction and wrapping around a first conductor structure. The semiconductor device includes a second concentric structure extending along the vertical direction and wrapping around a second conductor structure. The semiconductor device includes a third conductor structure extending along the vertical direction, wherein the third conductor structure is interposed between and spaced from the first and second concentric structures along a first lateral direction. The semiconductor device includes a fourth conductor structure extending along the first lateral direction. The fourth conductor structure at least partially wraps around each of the first concentric structure, the third conductor structure, and the second concentric structure.

In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect wires and vias arranged within one or more interconnect dielectric layers over a substrate. Further, a bottom electrode is disposed over the one or more interconnect wires and vias and comprises a first material having a first work function. A top electrode is disposed over the bottom electrode and comprises a second material having a second work function. The first material is different than the second material, and the first work function is different than the second work function. An anti-ferroelectric layer is disposed between the top and bottom electrodes.

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.

Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a first electrode comprising a first portion, a second portion, and a sheet portion connecting the first portion to the second portion. A ferroelectric material is over the sheet portion. A second electrode is over the ferroelectric material.

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

A semiconductor storage device includes a field-effect transistor, an interlayer insulation film, a source contact, an opening, and a capacitor. The field-effect transistor is provided on a semiconductor substrate. The interlayer insulation film is provided on the semiconductor substrate. The source contact runs through the interlayer insulation film and is electrically coupled to a source of the field-effect transistor. The opening is provided in a region of the interlayer insulation film including the source contact and allows the source contact to project therein. The capacitor includes a lower electrode, a ferroelectric film, and an upper electrode. The lower electrode is provided along an inside shape of the opening. The ferroelectric film is provided on the lower electrode. The upper electrode is provided on the ferroelectric film to fill the opening.