An elementary cell includes a device and a non-volatile resistive memory mounted in a series, the device including an upper selector electrode, a lower selector electrode, a layer made up of a first active material, referred to as an active selecting layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made of at least a second active material, referred to as an active memory layer, the active selecting layer being in a conductive crystalline state and the memory being in a very strongly resistive state that is more resistive than the strongly resistive state of the memory.

A memory device includes a plurality of first conductive lines on a substrate and extending in a first direction, a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction intersecting the first direction, and a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines. Each of the plurality of memory cells includes a switching element and a variable resistance material layer. The switching element includes a material having a composition of [Ge.sub.X P.sub.Y Se.sub.Z].sub.(1-W) [O].sub.W, where 0.15≤X≤0.50, 0.15≤Y≤0.50, 0.35≤Z≤0.70, and 0.01≤W≤0.10.

A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Provided are a switching device and a memory device including the switching device. The switching device includes first and second electrodes, and a switching material layer provided between the first and second electrodes and including a chalcogenide. The switching material layer includes a core portion and a shell portion covering a side surface of the core portion. The switching layer includes a material having an electrical resistance greater than an electrical resistance of the core portion, for example in at least one of the core portion or the shell portion.

Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

An electronic device comprising a semiconductor memory including at least one memory element is provided. The memory element comprises: a memory area for storing data; and a selection element electrically connected to the memory area and structured to include a first electrode layer, a second electrode layer, and a selection element layer that is interposed between the first electrode layer and the second electrode layer and includes an insulating material doped with a first dopant and a second dopant to form traps for trapping charge carriers, wherein an energy level of a trap formed by the first dopant is greater than an energy level of a trap formed by the second dopant.

Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.