Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.

A semiconductor integrated circuit device includes: a terminal; an internal resistor that is any one of a pull-up resistor configured so that a first end of the pull-up resistor is connected to the terminal and a first constant voltage is applied to a second end of the pull-up resistor, or a pull-down resistor configured so that a first end of the pull-down resistor is connected to the terminal and a ground voltage is applied to a second end of the pull-down resistor; and an AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.

A semiconductor integrated circuit device includes: a terminal; an internal resistor that is any one of a pull-up resistor configured so that a first end of the pull-up resistor is connected to the terminal and a first constant voltage is applied to a second end of the pull-up resistor, or a pull-down resistor configured so that a first end of the pull-down resistor is connected to the terminal and a ground voltage is applied to a second end of the pull-down resistor; and an AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.

A semiconductor device may include a first semiconductor structure including a gate structure and a stack, the gate structure including channel structures and the stack including a capacitor, and a second semiconductor structure that is bonded to the first semiconductor structure, the second semiconductor structure including a peripheral circuit. The capacitor may include conductive layers and dielectric layers that are alternately stacked along an internal surface of a trench that is formed within the stack.

A method of forming a capacitor structure includes a number of operations. A single carbon film is deposited over tops of bottom electrode plates. The single carbon film is patterned. The bottom electrode plates are etched based on the single carbon film after the single carbon film is patterned. The single carbon film is removed after the bottom electrode plates are etched. A dielectric layer is formed over the bottom electrode plates. A plurality of top electrode plates is formed over the dielectric layer and aligned with the bottom electrode plates.

Described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. Each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. A first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.

A computational device includes a phase-change material (PCM) variable microelectromechanical systems (MEMS) capacitor and a power source. The PCM variable MEMS capacitor includes a substrate, a first electrode, a second electrode, a PCM, and a heater. The first electrode is spaced apart from the substrate to define a PCM cavity. The second electrode is spaced apart from the first electrode to define a capacitance gap. The PCM is disposed within the PCM cavity. The heater element is coupled to receive a voltage pulse, whereby a temperature of the PCM varies to thereby vary the capacitance gap. The power source is coupled to the PCM variable MEMS capacitor and is operable to (i) supply the voltage pulse to the heater and (ii) a time-dependent voltage between the first electrode and the second electrode, to thereby implement a single multiply operation.

Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element.

A method of manufacturing a 3D device including: forming a first level including first transistors and a first interconnect; forming a second level including second transistors; overlaying the second level on the first level; and bonding the second level to the first level; the bonding includes performing metal region to metal region bonding, the 3D device includes at least four electronic circuits (AL4ECs) and at least one redundancy circuit, where the AL4ECs each include a first circuit which includes a portion of the first transistors, where the AL4ECs include a second circuit which includes a portion of the second transistors, where the AL4ECs each include a vertical connectivity structure (VCSt), the VCSt includes pillars, where the pillars are configured to provide electrical connections between the first circuit and the second circuit, and where the AL4ECs each include at least one memory control circuit and at least one memory array.