A semiconductor device includes a semiconductor body having opposing first and second surfaces along a vertical direction, and a bipolar junction transistor that includes an emitter region electrically connected to an emitter contact at the first surface, a base region electrically connected to a base contact at the first surface, and a collector region electrically connected to a collector contact. A dielectric isolation structure extends into the semiconductor body from the first surface and includes a first sub-structure arranged, along a first lateral direction, between the emitter contact and the base contact. A field plate structure including a field plate dielectric and a field plate electrode is arranged on the field plate dielectric. A first part of the field plate structure is arranged on the first surface of the semiconductor body. A second part of the field plate structure is arranged on the first sub-structure of the dielectric isolation structure.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.