Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.

Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.

A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.

An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.

A bipolar junction transistor includes a first well region having a first conductive type, a second well region disposed adjacent to the first well region and having a second conductive type, an emitter disposed on the first well region and having the second conductive type, a base disposed on the first well region and having the first conductive type, a collector disposed on the second well region and having the second conductive type, and device isolation regions disposed among the emitter, the base and the collector. Particularly, the emitter, the base and the collector are spaced apart from the device isolation regions.

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

A semiconductor device including: a P-type base region provided; an N-type emitter region provided inside the P-type base region; a P-type collector region that is provided on the surface layer portion of the N-type semiconductor layer and is separated from the P-type base region; a gate insulating film that is provided on the surface of the N-type semiconductor layer, and that contacts the P-type base region and the N-type emitter region; a gate electrode on the gate insulating film; a pillar shaped structure provided inside the N-type semiconductor layer between the P-type base region and the P-type collector region, wherein one end of the pillar shaped structure is connected to an N-type semiconductor that extends to the surface layer portion of the N-type semiconductor layer, and the pillar shaped structure includes an insulator extending in a depth direction of the N-type semiconductor layer.

According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.