A hetero-junction bipolar transistor includes an n-type collector layer made of InGaN, a base layer formed on the collector layer and made of GaN, and an emitter layer formed on the base layer and made of a nitride semiconductor containing Al, in which the collector layer, the base layer, and the emitter layer are formed in a state in which the principal surface is a group V polar plane. The base electrode can be formed in contact with the upper part of the base layer around the emitter layer formed in a mesa shape.

An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.

A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.

The present disclosure generally relates to dopant profile control in a heterojunction bipolar transistor (HBT). In an example, a semiconductor device structure includes a semiconductor substrate and an HBT. The HBT includes a collector region, a base region, and an emitter region. The base region is disposed on or over the collector region. The emitter region is disposed on or over the base region. The base region is disposed on or over the semiconductor substrate and includes a heteroepitaxial sub-layer. The heteroepitaxial sub-layer is doped with a dopant. A concentration gradient of the dopant increases from a region in a layer adjoining and overlying the heteroepitaxial sub-layer to a peak concentration in the heteroepitaxial sub-layer without decreasing between the region and the peak concentration.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

A heterojunction bipolar transistor and a base-collector grade layer. The heterojunction bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, a base-collector grade layer and an emitter layer. The sub-collector layer is disposed on the substrate. The collector layer is disposed over the sub-collector layer. The base layer is disposed over the collector layer. The base-collector grade layer is disposed between the base layer and the collector layer, and includes at least two stacked periodic structures. Each periodic structure includes an In.sub.0.53Ga.sub.0.47As layer and an Al.sub.xGa.sub.yIn.sub.1-x-yAs layer stacked on the In.sub.0.53Ga.sub.0.47As layer. The range of x is 0.040.44, the range of y is 0.440.04, and the thickness of the Al.sub.xGa.sub.yIn.sub.1-x-yAs layer is 0.6 nm1.8 nm. The emitter layer is disposed on the base layer.

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 310.sup.16 cm.sup.3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHZ. Other embodiments of the module are provided along with related methods and components thereof.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.