A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450 C. to 1200 C., and forming a first load terminal structure at the first side of the semiconductor body.

A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

A method of manufacturing a semiconductor device includes: forming field electrode structures extending in a direction vertical to a first surface in a semiconductor body; forming cell mesas from portions of the semiconductor body between the field electrode structures, including body zones forming first pn junctions with a drift zone; forming gate structures between the field electrode structures and configured to control a current flow through the body zones; and forming auxiliary diode structures with a forward voltage lower than the first pn junctions and electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.

A semiconductor device includes a drift region extending from a first surface into a semiconductor portion. A body region between two portions of the drift region forms a first pn junction with the drift region. A source region forms a second pn junction with the body region. The pn junctions include sections perpendicular to the first surface. Gate structures extend into the body regions and include a gate electrode. Field plate structures extend into the drift region and include a field electrode separated from the gate electrode. A gate shielding structure is configured to reduce a capacitive coupling between the gate structures and a backplate electrode directly adjoining a second surface.

A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 m in regard to the depth direction from the rear surface of the semiconductor substrate.

Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source region is formed by deposition, and a trench-shaped contact hole is used at the source region, in order to attain low contact resistance and small cell pitch. The present invention may also be implemented in an IGBT.

There are disclosed herein various implementations of a latch-up free power transistor. Such a device includes an insulated gate situated adjacent to a conduction channel in the power transistor, an emitter electrode in direct physical contact with the conduction channel, and a collector electrode in electrical contact with the conduction channel. The power transistor also includes an emitter layer in contact with a surface of a semiconductor substrate adjacent the conduction channel.

A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 m in regard to the depth direction from the rear surface of the semiconductor substrate.

A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region.