A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.

A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.

Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate insulating layer disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.

A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.