A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

An IGBT device includes a drift region of a first doping type; a plurality of pillar regions of the second doping type, disposed at intervals in the lateral direction within the drift region; and a transition layer of the first doping type, connected under the pillar region. The thickness of the transition layer is larger than 2 microns and less than or equal to 11 microns, and the doping concentration of the transition layer ranges from larger than or equal to 2.410.sup.14/cm.sup.3 to less than or equal to 2.410.sup.16/cm.sup.3, in order to solve the technical problem of a large turn-off energy loss due to the tail current of the conventional SJ-IGBT device in the turn-off stage.

An IGBT includes, in a single chip, an active region configured to conduct a forward load current between first and second load terminals at different sides of a semiconductor body. The active region is separated into at least first and second IGBT regions. At least 90% of the first IGBT region is configured to conduct, based on a first control signal, the forward load current. At least 90% of the second IGBT region is configured to conduct, based on a second control signal, the forward load current. A first MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of first IGBT region. A second MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS-channel-conductivity-to-area-ratio amounts to less than 80% of the first MOS-channel-conductivity-to-area-ratio.

A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.

An RC IGBT includes, in a single chip, an active region configured to conduct both a forward load current and a reverse load current between a first load terminal at a front side of a semiconductor body of the RC IGBT and a second load terminal at a back side of the semiconductor body. The active region is separated into at least: an IGBT-only region, at least 90% of which is configured to conduct, based on a first control signal, only the forward load current; an RC IGBT region, at least 90% of which is configured to conduct the reverse load current and, based on a second control signal, the forward load current; and a hybrid region, at least 90% of which is configured to conduct, based on both the first control signal and the second control signal, the forward load current.

An RC IGBT includes, in a single chip, an active region configured to conduct both a forward load current and a reverse load current between a first load terminal at a front side of a semiconductor body of the RC IGBT and a second load terminal at a back side of the semiconductor body. The active region is separated into at least an IGBT-only region and an RC IGBT region. At least 90% of the IGBT-only region is configured to conduct, based on a first control signal, only the forward load current. At least 90% of the RC IGBT region is configured to conduct the reverse load current and, based on a second control signal, the forward load current.

A semiconductor device is proposed. The semiconductor device includes trenches extending into a semiconductor body from a first main surface. A first group of the trenches includes a gate electrode. A second group of the trenches includes a source electrode, the source electrode being subdivided into at least a first part and a second part. A conductance per unit length of the first part along a longitudinal direction of the source electrode is smaller than a conductance per unit length of the second part along the longitudinal direction of the source electrode, the second part being electrically coupled to a source contact area via the first part. A mesa region bounded by a trench of the first group and a trench of the second group includes a source region electrically connected to the source contact area.

A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.

A semiconductor device including a semiconductor substrate having an upper surface and a lower surface is provided. In a depth direction connecting the upper and lower surfaces of the semiconductor substrate, a donor concentration distribution includes a first donor concentration peak at a first depth, a second donor concentration peak at a second depth between the first donor concentration peak and the upper surface, a flat region between the first donor concentration peak and the second donor concentration peak, and a plurality of donor concentration peaks between the first donor concentration peak and the lower surface. The second donor concentration peak has a lower concentration than the first donor concentration peak. The donor concentration distribution in the flat region is substantially flat. The thickness of the flat region in the depth direction is 10% or more of the thickness of the semiconductor substrate.

Provided is a semiconductor device comprising a diode portion, comprising: a plurality of trench portions provided at a front surface of a semiconductor substrate; a drift region of a first conductivity type provided on the semiconductor substrate; an anode region of a second conductivity type provided above the drift region in the diode portion; a first plug region of the second conductivity type provided above the drift region in the diode portion, which has a doping concentration higher than a doping concentration of the anode region; a front surface side electrode provided above the semiconductor substrate; and an interlayer dielectric film provided above a mesa portion provided between the plurality of trench portions; wherein the anode region is connected to the front surface side electrode on side surfaces of the plurality of trench portions.