According to an embodiment, the semiconductor device (100) comprises a semiconductor body (1) with a first side (10) and a second side (20) opposite to the first side. The semiconductor device further comprises a first thyristor structure (I) and a second thyristor structure (II). The second thyristor structure is arranged laterally beside the first thyristor structure. Each of the first and the second thyristor structure comprises a first base region (11a, 11b) at the first side and agate electrode (1a, 1b) on the first side adjoining the assigned first base region. The first base regions of the two thyristor structures are regions of the semiconductor body and are of the same conductivity type. The gate electrodes of the thyristor structures are individually and independently electrically contactable.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.

A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.

A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 110.sup.15/cm.sup.3.

The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

A turn-off power semiconductor device includes first and second thyristor cells, a common gate contact and a plurality of stripe-shaped electrically conductive first gate runners. Each first gate runner has a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion. The first end portion is directly connected to the common gate contact. The first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer. The second gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer. The first gate electrode layer is directly connected to the common gate contact. At least the first connecting portion of each first gate runner is separated from the first gate electrode layer.

A turn-off power semiconductor device includes first and second thyristor cells, a common gate contact and a plurality of stripe-shaped electrically conductive first gate runners. Each first gate runner has a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion. The first end portion is directly connected to the common gate contact. The first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer. The second gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer. The first gate electrode layer is directly connected to the common gate contact. At least the first connecting portion of each first gate runner is separated from the first gate electrode layer.

Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.