A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.