The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A method for producing a device comprising GAA transistors. Advantageously, the channels of the transistors are produced by deposition of a semiconductor material, preferably a 2D material, after successive removal of certain layers of the initial stack. The gates-all-around are produced after selective removal of the other layers from the initial stack. The initial stack does not comprise the semiconductor material, nor the material of the gates. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material.

There is provided a transistor comprising: a graphene layer structure provided on a non-metallic surface of a substrate, the graphene layer structure having an insulating cap; a source contact provided in contact with a first edge of the graphene layer structure; an insulator provided in contact with an opposite, second edge of the graphene layer structure; a drain contact provided in contact with the insulator, whereby there is a distance of least separation between the drain contact and the graphene layer structure along the second edge of the graphene layer structure and through the insulator; and a gate contact provided (i) over the graphene layer structure and separated therefrom by the insulating cap and/or (ii) under the graphene layer structure and separated therefrom by substrate.

The invention relates to a device comprising transistors (T1, T2, T3), each comprising: a channel (41) with the basis of a semiconductive material, a gate-all-around (50), totally surrounding said channel (41), a source (42) and a drain (43) on either side of the channel (41), and source and drain contacts (60S, 60, 60D), a gate dielectric layer (30) separating the channel (41) and the gate-all-around (50), spacers (70) on either side of the gate (50). Advantageously, the gate dielectric layer (30) and the spacers (70) are formed by at least one single and same continuous layer (73) surrounding the gate-all-around (50). The invention also relates to a method for producing such a device.

Disclosed are a high-mobility atomic layer semiconductor device based on modulation doping and a method for fabricating the same, which prevent a charge scattering phenomenon caused by ionized impurities by modulation doping dopants such that the dopants are spatially separated from a channel layer of an atomic layer semiconductor device having an atomic layer semiconductor heterojunction structure band-aligned. According to an embodiment of the present disclosure, a high-mobility atomic layer semiconductor device based on modulation doping includes a substrate, an atomic layer semiconductor heterojunction structure band-aligned in type I or type II and including a channel layer allowing movement of an electron and a doping layer, wherein the channel layer and the doping layer are stacked on the substrate, and a dopant formed on the doping layer and including a material for supplying an electron or a hole to the channel layer. The dopant is doped while being spatially separated from the channel layer through the doping layer, instead of being directly doped into the channel layer.

Provided are a method for preparing a nanotube array, a nanotube array and a device. The method includes: preparing a double-layer two-dimensional material with a relative angle of lattice orientations, which is used as a template; determining the chiral parameters of nanotubes to be prepared corresponding to the relative angle of the lattice orientations of the double-layer two-dimensional material, determining a nanoribbon orientation and a nanoribbon width according to the determined chiral parameters, determining the inter-nanoribbon spacing according to the density of the nanotubes to be prepared and the nanoribbon width, and etching the double-layer two-dimensional material according to the determined nanoribbon orientation, nanoribbon width and inter-nanoribbon spacing to obtain a nanoribbon array of the double-layer two-dimensional material; and performing thermal excitation treatment on the obtained nanoribbon array of the double-layer two-dimensional material to obtain a nanotube array. The present disclosure can prepare a nanotube array with controllable density, orientation and chirality.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate (101) and a first electrode (102) configured as either a source or a drain of the transistor. The device includes a second electrode (104) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer (103) that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion (107) and a gate insulating layer (106), which is arranged between the active layer (103) and a gate conductor portion (107) so as to prevent direct contact between the active layer (103) and the gate conductor portion (107). The active layer (103) comprises a 1D material arranged with its longitudinal axis parallel to the substrate (101) and/or a 2D material arranged with its plane substantially parallel to the substrate (101) The present disclosure further comprises a method (3000) for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

A semiconductor structure includes: a substrate, a channel layer and a barrier layer which are stacked sequentially, the channel layer and the barrier layer including a gate region, and a source region and a drain region which are located on two sides of the gate region; a p-type semiconductor layer, located in the gate region; a first hydrogen-rich layer, located on a side, close to the drain region, of the p-type semiconductor layer, a hydrogen concentration of the first hydrogen-rich layer being greater than a hydrogen concentration of the p-type semiconductor layer; a gate, a source and a drain, where the gate is located on a side, away from the substrate, of the p-type semiconductor layer, the source is located in the source region, and the drain is located in the drain region.

A method for making a semiconductor device may include forming a stack of alternating gate and nanostructure layers above a substrate, and forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

A semiconductor device may include a substrate, a stack of alternating gate and nanostructure layers above the substrate, and a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.