Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a method of fabricating a semiconductor structure comprises providing a FET structure disposed above a substrate, the FET structure comprising a vertical metal gate structure disposed between a pair of source/drain (S/D) epitaxial (EPI) structures and having a set of vertically-stacked, horizontal nanosheets extending through the vertical metal gate structure in the first horizontal direction to electrically connect the S/D EPI structures to each other. The method further comprises removing the substrate, removing the portion of vertical metal gate structure below the bottom-most nanosheet, removing at least enough of the bottom-most nanosheet to sever the its electrical conducting path between the S/D EPI structures, and filling the void created by the removed gate metal and nanosheet with a dielectric material that also covers the bottom surfaces of the S/D EPI structures.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a vertical metal gate disposed between a first and second source/drain (S/D) epitaxial (EPI) structure and having a set of vertically-stacked, horizontal channels, all but the top channel connecting the first and second S/D EPI structures through the vertical metal gate. A high-K dielectric material is disposed between the vertical metal gate and each of the horizontal channels, and vertical spacer layers separate the vertical metal gate from the S/D EPI structures. A low-K dielectric structure is disposed above the top-most portion of the vertical metal gate and fills a recess above the vertical metal gate and between the first vertical spacer layer and the second vertical spacer layer.

An integrated circuit device includes: a fin-type active region on a substrate; a nanosheet disposed on the fin-type active region; a gate line surrounding the nanosheet, wherein the gate line overlaps the nanosheet; a source/drain region disposed on the fin-type active region and contacting the nanosheet; and an interface insulating film surrounding the gate line, and including an inner spacer portion disposed between a sidewall of the gate line and the source/drain region, wherein the inner spacer portion includes: a first inner spacer portion protruding toward the source/drain region, while covering the sidewall of the gate line and while spaced apart from the nanosheet, wherein the first inner spacer portion has a first thickness; and a second inner spacer portion extending from the first inner spacer portion toward the nanosheet, wherein the second inner spacer portion has a second thickness that is less than the first thickness.

A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.

A semiconductor structure and a method for forming the same, where the semiconductor structure includes a substrate; a channel layer structure suspended above the substrate, where in the vertical direction, the channel layer structure includes one or more spaced channel layers; a repair layer covering the surfaces of the channel layers; and a gate structure located on the substrate and spanning the channel layer structure, where the gate structure surrounds the channel layers along the extension direction of the gate structure and covers the repair layer.

Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes a fluorine concentration that decreases from the inner surface and the outer surface towards a center of the first gate spacer. The structure further includes a second gate spacer disposed on the outer surface of the first gate spacer, and the second gate spacer includes a fluorine concentration that decreases from an outer surface towards an inner surface.

A semiconductor device includes a semiconductor substrate, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a dielectric wall, and a first isolation feature. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure are disposed on the semiconductor substrate. The first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure. The dielectric wall is disposed on the semiconductor substrate and is connected between the first semiconductor structure and the second semiconductor structure. The first isolation feature is disposed between the first semiconductor structure and the third semiconductor structure, and extends into the semiconductor substrate.