Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one semiconductor layer and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate. The dielectric layer structure includes a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.

A semiconductor device includes: a gate structure having a side in a first direction and extending in a second direction intersecting the first direction; a source/drain region on the side of the gate structure; a plurality of channel layers spaced apart from each other in a third direction intersecting the first direction and the second direction and surrounded by the gate structure; and a plurality of inner spacers between the gate structure and the source/drain region, wherein the plurality of inner spacers have respective heights in the third direction increasing in the third direction toward bottom, and have respective thicknesses in the first direction decreasing in the third direction toward bottom.

A semiconductor device may include a substrate, a lower power line in a lower portion of the substrate, metal layers on the substrate, and a protection structure that is electrically connected to the lower power line and the metal layers. The protection structure may include a doping pattern in the substrate, and a first source/drain pattern that is on the substrate and is electrically connected to an upper portion of the doping pattern. The doping pattern and the first source/drain pattern may include different dopants from each other.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer has an edge portion and a center portion, and a height of the center portion is substantially greater than a height of the edge portion. The structure further includes a dielectric spacer disposed below and in contact with the edge portion of the first semiconductor layer, a gate dielectric layer surrounding the center portion of the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.

A semiconductor device includes: a substrate; source/drain patterns on the substrate; a channel pattern between the source/drain patterns, the channel pattern including a plurality of semiconductor patterns; a gate electrode between the plurality of semiconductor patterns; an upper separation structure extending in a first direction and spaced apart from the gate electrode in a second direction intersecting the first direction; a first backside separation structure penetrating the substrate below the gate electrode in a third direction intersecting the first direction and the second direction; and a second backside separation structure penetrating the substrate and overlapping the upper separation structure in the third direction.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one of the semiconductor layers and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate, the dielectric layer structure comprising a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer, and a bottom surface of the S/D feature, the first dielectric layer, the second dielectric layer, and the inner spacer define an air gap therebetween.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent gates around subsets of nanoribbons in the stack. In previous nanoribbon transistors, a gate electrode wraps around all of the semiconductor regions and spans the areas between adjacent semiconductor regions, thus electrically coupling the centers of the semiconductor regions. To achieve a stack of semiconductor regions with independent gates, adjacent nanoribbons in the stack may be set at different distances apart, or two or more sacrificial materials may be included when forming the stack of semiconductor materials and selectively etched when forming different gates.