A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.

An electronic device having one or more non-planar transistors is disclosed. At least one of the non-planar transistors comprises: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one gate spacer of the one or more gate spacers having a multi-layer dielectric structure comprising an interior wall disposed next to a respective gate structure of the one or more gate structures, wherein the interior wall is formed from a first dielectric material, an exterior wall spaced apart from the interior wall, wherein the exterior wall is formed from a second dielectric material, and a third dielectric material disposed between the interior wall and the exterior wall, wherein a dielectric constant of the third dielectric material is lower than both the dielectric constants of the first and second dielectric materials.

A semiconductor structure and fabrication method is provided for gate all around (GAA) nanosheet devices. The semiconductor structure comprises a substrate, a gate stack on the substrate with a plurality of gate regions and silicon-based channel regions alternatingly arranged one on the other. A length of the gate regions is smaller than a length of the channel regions. Thus, pockets are formed on a side of the gate stack, each pocket being arranged next to one gate region and between the two channel regions adjacent to the gate region. Further, a silicon-based first contact region extends in a distance to the side of the gate stack, and a silicon-based filler material is arranged between the first contact region and the first side of the gate stack and in each first pocket.

The present disclosure provides a method for forming a semiconductor structure. The method includes forming a layer stack on a substrate. The layer stack includes a first sub-stack, and a second sub-stack on the first sub-stack. The second sub-stack includes a plurality of sacrificial layers alternating between first and second sacrificial layers, wherein neighboring first and second sacrificial layers of the second sub-stack are separated by a liner layer. The layer stack also includes a third sub-stack on the second sub-stack. The method further includes forming recesses in the layer stack, forming inner spacers in the recesses, removing the at least one second sacrificial layer of the second sub-stack by etching, thereby forming at least one first cavity, and filling the at least one first cavity with dielectric material thereby forming at least one dielectric layer.

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.

A semiconductor device includes: a gate structure having a side in a first direction and extending in a second direction intersecting the first direction; a source/drain region on the side of the gate structure; a plurality of channel layers spaced apart from each other in a third direction intersecting the first direction and the second direction and surrounded by the gate structure; and a plurality of inner spacers between the gate structure and the source/drain region, wherein the plurality of inner spacers have respective heights in the third direction increasing in the third direction toward bottom, and have respective thicknesses in the first direction decreasing in the third direction toward bottom.

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

An integrated circuit device includes: a fin-type active region on a substrate; a nanosheet disposed on the fin-type active region; a gate line surrounding the nanosheet, wherein the gate line overlaps the nanosheet; a source/drain region disposed on the fin-type active region and contacting the nanosheet; and an interface insulating film surrounding the gate line, and including an inner spacer portion disposed between a sidewall of the gate line and the source/drain region, wherein the inner spacer portion includes: a first inner spacer portion protruding toward the source/drain region, while covering the sidewall of the gate line and while spaced apart from the nanosheet, wherein the first inner spacer portion has a first thickness; and a second inner spacer portion extending from the first inner spacer portion toward the nanosheet, wherein the second inner spacer portion has a second thickness that is less than the first thickness.

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

A semiconductor structure is provided. The semiconductor structure includes a first set of nanostructures that are stacked vertically and spaced apart from one another and formed in a first well, a source/drain feature adjoining the first set of nanostructures, a first top gate electrode layer above a topmost nanostructure in the first set of nanostructures, and an inner gate electrode layer sandwiched between the nanostructures. A first dimension of the inner gate electrode layer in a first direction is greater than a second dimension of the first top gate electrode layer in the first direction.