A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) nanosheet structure includes performing a trim back recess process to form recesses in inner spacers of a fin-shaped column in a first direction from a sidewall of the fin-shaped column, wherein the fin-shaped column includes a stack of nanosheet channels and sacrificial layers having the inner spacers on both sides thereof in the first direction, performing an interface epitaxial growth process to grow interface source/drain (S/D) epi layers from exposed surfaces of the nanosheet channels of the fin-shaped column on the sidewalls of the fin-shaped column, performing an etch back process to etch back the interface S/D epi layer and form a continuous surface of the interface S/D epi layer, and performing a full epitaxial growth process to fully grow an S/D epi layer from the continuous surface of the interface S/D epi layer.

A method of manufacturing step of a device having a gate and a silicon substrate that are insulation-isolated from each other. In the method, germanium compositions of a silicon germanium sacrificial layer for forming a stacked channel and a germanium composition of a silicon germanium sacrificial layer for insulation-isolating the gate and the substrate are not changed. After the stacked film is etched, a protective dielectric film is formed on a sidewall of the stacked film, which is repeated using different protective film materials. Thereafter, a silicon sacrificial layer and a silicon germanium sacrificial layer remaining in a lower portion are removed by isotropic etching to form a region in which the insulating isolation film is embedded. The steps from the formation of the stacked film of the protective dielectric films to the removal of the sacrificial layer by etching in the continuous process use the same apparatus.

Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.

A semiconductor device structure is provided. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, a plurality of semiconductor layers vertically stacked over the substrate, wherein the gate electrode layer surrounds a portion of each of the semiconductor layers, a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface, and a dielectric spacer disposed between two adjacent semiconductor layers of the plurality of semiconductor layers, wherein the dielectric spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the dielectric spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface.

The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. The method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. The recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.

The present disclosure provides a method of manufacturing a stacked nanosheet gate-all-around field-effect transistor and a field-effect transistor. The method includes: forming a stack on a substrate, the stack includes multiple nanosheet layers and multiple silicon alloy layers alternately stacked; etching each silicon alloy layer to form a first cavity, the first cavity is between two adjacent nanosheet layers; manufacturing a protective layer in the first cavity, the protective layer covers an inner surface of the first cavity and is recessed to form a second cavity; manufacturing a gate electrode and two source/drain electrodes based on the second cavity, an air spacer is between the gate electrode and any source/drain electrode; and removing a first dielectric constant medium in a first space, the first space is in the air spacer and surrounded by an upper surface of the uppermost nanosheet layer, the gate electrode and any source/drain electrode.

A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.

The semiconductor device includes active patterns on a substrate, each of the active patterns extending in a first direction, and an isolation pattern is on at least a portion of respective sidewalls of each of the active patterns, a gate structure on the active patterns and on the isolation pattern, the gate structure extending in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction, a mask pattern on the gate structure, a sidewall of the mask pattern is aligned with a sidewall of the gate structure, and a division pattern on the isolation pattern, the division pattern in contact with the sidewall of the gate structure and the sidewall of the mask pattern.