A semiconductor device includes an insulating base layer, a plurality of semiconductor patterns stacked on the insulating base layer and spaced apart from each other, a gate structure surrounding the plurality of semiconductor patterns, first and second source/drain patterns disposed on the insulating base layer and connected to both side surfaces of the plurality of semiconductor patterns, respectively, a contact structure connected to first source/drain patterns through the insulating base layer, a sidewall insulating film disposed between an upper portion of the contact structure and an upper portion of the insulating base layer and extending onto a region of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns, and a power transmission line disposed on a lower surface of the insulating base layer and connected to the contact structure.

A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

A semiconductor device includes a backside power delivery network (BSPDN). The semiconductor device includes a substrate, a first active pattern extending in a first direction, on a top surface of the substrate, a second active pattern extending in the first direction, and spaced apart from the first active pattern in a second direction intersecting the first direction, on the top surface of the substrate, a gate structure extending in the second direction, on the first active pattern and the second active pattern, a first source/drain pattern connected to the first active pattern, on a side surface of the gate structure, a second source/drain pattern connected to the second active pattern, on the side surface of the gate structure, back source/drain contacts penetrating the substrate, and a first power line connected to the back source/drain contacts on a bottom surface of the substrate.

Structures having stacked transistors with backside access are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer including first, second, third and fourth stacks of nanowires and corresponding first, second, third and fourth overlying gate lines, and the device layer including first, second, third, fourth and fifth source or drain structures and corresponding overlying trench contacts alternating with the stacks of nanowires and the overlying gate lines, and one or more metallization layers above the device layer. A backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure isolated from a top portion of the third source or drain structure.

An integrated circuit device may includes a plurality of device isolation layers extending lengthwise in a first horizontal direction, a plurality of gap-fill insulation layers arranged apart from one another in the first horizontal direction, a plurality of gate structures extending lengthwise in a second horizontal direction perpendicular to the first horizontal direction and on the plurality of gap-fill insulation layers, a first source/drain region and a second source/drain region respectively disposed at both sides of a first gate structure among the plurality of gate structures with respect to the first horizontal direction, an insulation block under the first source/drain region, and an insulation barrier between the first source/drain region and the insulation block. The insulation barrier may cover a lower surface of the first source/drain region.

A semiconductor device includes a first source/drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source/drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.

There is provided a method for forming a semiconductor device. The method comprising performing frontside processing comprising forming a transistor structure on a frontside of a substrate, the transistor structure comprising a first source/drain body and a second source/drain body located in a first and a second source/drain region, respectively, and a channel structure between the first source/drain body and the second source/drain body, wherein the first source/drain body and the second source/drain body have a first doping concentration. The method also includes, subsequent to the frontside processing, performing backside processing comprising exposing the first source/drain body from a backside of the substrate, and processing the first source/drain body to form, in the first source/drain region, a replacement source/drain body having a second doping concentration different from the first doping concentration.

A semiconductor device includes a fin stack, a gate structure on the fin stack, a source region on a first side of the gate structure, a drain region on a second side of the gate structure opposite the first side, and a source contact extending to and connecting the source region. The source region and the drain region are asymmetric.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a method of fabricating a semiconductor structure comprises providing a FET structure disposed above a substrate, the FET structure comprising a vertical metal gate structure disposed between a pair of source/drain (S/D) epitaxial (EPI) structures and having a set of vertically-stacked, horizontal nanosheets extending through the vertical metal gate structure in the first horizontal direction to electrically connect the S/D EPI structures to each other. The method further comprises removing the substrate, removing the portion of vertical metal gate structure below the bottom-most nanosheet, removing at least enough of the bottom-most nanosheet to sever the its electrical conducting path between the S/D EPI structures, and filling the void created by the removed gate metal and nanosheet with a dielectric material that also covers the bottom surfaces of the S/D EPI structures.