A method of manufacturing a semiconductor device includes at least the following steps. An opening is formed in a substrate. A first protection layer is formed on an exposed surface of the opening. A first etching process is performed on the opening with the first protection layer thereon, to simultaneously remove the first protection layer on a sidewall of the opening and a portion of the substrate to deepen a depth of the opening.

In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

A high voltage transistor may include a plurality of source/drain regions, a gate structure, and a gate oxide layer that enables the gate structure to selectively control a channel region between the source/drain regions. The gate oxide layer may extend laterally outward toward one or more of the plurality of source/drain regions such that at least a portion of the gate oxide layer is not under the gate structure. The gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used as a self-aligned structure for forming the source/drain regions of the high voltage transistor. In particular, the gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used to form the source/drain regions at a greater spacing from the gate structure without the use of additional implant masks when forming the source/drain regions.

In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first and a second fin-shaped active region over a substrate, the first and second fin-shaped active regions extending lengthwise along a first direction, forming a gate structure over channel regions of the first and second fin-shaped active regions, the gate structure extending lengthwise along a second direction substantially perpendicular to the first direction, forming a trench to separate the gate structure into two segments, the trench extending lengthwise along the first direction and being disposed between the first and second fin-shaped active regions, performing an etching process to enlarge an upper portion of the trench, and forming a gate isolation structure in the trench, and, in a cross-sectional view cut through both the first and second fin-shaped active regions and the gate structure, the gate isolation structure is a T-shape structure.

N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.