The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor (EDMOS) field effect transistor (FET) with a fully depleted region comprising a dual thicknesses semiconductor material and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness; a gate structure on the SOI material over the first portion with the first thickness; and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness.

Semiconductor devices including a nitrogen doped field relief dielectric layer are described. The microelectronic device comprises a substrate including a body region having a first conductivity type and a drain drift region having a second conductivity type opposite the first conductivity type; a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region and a doped field relief dielectric layer on the drift region. Doping of the field relief dielectric layer with nitrogen raises the dielectric constant of the field relief dielectric above that of pure silicon dioxide. Increasing the dielectric constant of the field relief dielectric layer may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance of the microelectronic device compared to a microelectronic device of similar size with a field relief dielectric which is not doped with nitrogen.

According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a substrate, a source region, a drain region and a gate structure. The source region is located in the substrate. The drain region is located in the substrate. The gate structure is disposed on the substrate and located between the source region and the drain region, and includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is adjacent to the source region and includes a first sub-gate insulating layer. The second sub-gate structure is adjacent to the drain region and includes a second sub-gate insulating layer. The second sub-gate insulating layer and the first sub-gate insulating layer are separated from each other. The first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness greater than the first thickness.

A dielectric film, which contacts a field plate electrode, is formed between the field plate electrode and a gate electrode, and a recess is formed at an upper surface of the dielectric film and between a drain region and the gate electrode.

A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body.

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

A method of etching for a semiconductor structure having a substrate, and a first structure located on part of a top surface of the substrate, where two side surfaces of the first structure are configured as sidewalls, can include: forming an insulation layer to cover the substrate, the first structure, and the sidewalls; performing a dry etching process to etch a first portion of the insulation layer; and performing a wet etching process to etch a remaining portion of the insulation layer, in order to expose the top surface of the substrate, where a thickness of the first portion of the insulation layer etched by the dry etching process is greater than a thickness of the remaining portion of insulation layer etched by the wet etching process, in order to decrease formation of cavity in the substrate and/or sidewalls.

An LDMOS transistor can include: a field oxide layer structure adjacent to a drain region; and at least one drain oxide layer structure adjacent to the field oxide layer structure along a lateral direction, where a thickness of the drain oxide layer structure is less than a thickness of the field oxide layer, and at least one of a length of the field oxide layer structure and a length of the drain oxide layer structure is adjusted to improve a breakdown voltage performance of the LDMOS transistor.

In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.