An oxide thin film transistor, a preparation method thereof, and an electronic device are provided. The oxide thin film transistor includes a base substrate, a gate electrode and a metal oxide semiconductor layer, a gate insulation layer arranged between the metal oxide semiconductor layer and the gate electrode; the gate insulation layer includes a silicon oxide insulation layer and a silicon nitride layer, the silicon nitride layer adopts a single-layer structure or include a plurality of silicon nitride sublayers which are sequentially stacked, the silicon oxide insulation layer is between the silicon nitride layer and the metal oxide semiconductor layer; at least a part of a region in the silicon nitride layer satisfies that the percentage content of SiH bonds in the sum of SiN bonds, NH bonds and SiH bonds is not more than 7.

The invention relates to a microelectronic device comprising a transistor (T1, T2) comprising

at least two channels (41a, 41b, 41c) stacked along a main direction (z),. a first gate (G1) partially surrounding one of the channels (41a, 41b, 41c),

a second gate (G2) partially surrounding said channel (41),

a source (42) and a drain (43) either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and to the drain (43),

a gate dielectric layer (70, 71, 72) separating each channel (41) of the gates-all-around (G1, G2).

The first and second gates (G1, G2) are isolated from one another, such that they can be independently biased.

The invention also relates to a method for producing such a device.

One aspect of the invention relates to a field effect transistor (3) comprising: a channel region (11); a source region (12) and a drain region (13); a gate structure (14) comprising: a gate dielectric layer (14b); a gate electrode (14a) with a first work function (W.sub.1); and a lateral gate conductor (14c) disposed at least against the flank of the gate electrode (14a) located on the side of the drain region (13), the lateral gate conductor (14c) extending to the gate dielectric layer (14b) in direct contact with the gate electrode (14a) and having a second work function (W.sub.2);
the second work function (W.sub.2) being: strictly greater than the first work function (W.sub.1) when the transistor is of type p; strictly lower than the first work function (W.sub.1) when the transistor is of type n.

A thin film transistor and a display apparatus including the thin film transistor are provided. The thin film transistor includes a first gate electrode, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, and a second gate electrode on the second gate insulating layer, wherein the active layer includes a channel portion, and the channel portion includes a first channel portion overlapping the first gate electrode and a second channel portion overlapping the second gate electrode, and wherein the first gate electrode and the second gate electrode do not overlap each other in a plan view.

A semiconductor device including a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer in contact with the first conductive layer and the second conductive layer, a third conductive layer over the first insulating layer, a semiconductor layer in contact with the third conductive layer, the first conductive layer, and the first insulating layer, a second insulating layer over the first insulating layer, the semiconductor layer, and the third conductive layer, and a fourth conductive layer over the second insulating layer is provided. A shortest distance from a top surface of the first conductive layer to a top surface of the second conductive layer is longer than a shortest distance from the top surface of the first conductive layer to a bottom surface of the fourth conductive layer.

A semiconductor device (200) includes an oxide (230) over a substrate: a first conductor (242a1) and a second conductor (242b1) that are over the oxide and separated from each other; a third conductor (242a2) in contact with a part of a top surface of the first conductor; a fourth conductor (242b2) in contact with a part of a top surface of the second conductor; a first insulator (271a, 271b) that is positioned over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor; a second insulator (255) that is positioned in the opening of the first insulator and in contact with another part of the top surface of the first conductor, another part of the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator (250) that is positioned in the opening of the first insulator and in contact with a top surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second conductor; and a fifth conductor that is positioned over the third insulator in the opening of the first insulator and includes a region overlapping with the oxide with the third insulator therebetween. A distance (L2) between the first conductor and the second conductor is smaller than a distance (L1) between the third conductor and the fourth conductor.

A transistor with a small variation in electrical characteristics is to be provided. The transistor includes first to fourth conductors, first to tenth insulators, and an oxide. The third to fifth insulators are positioned over the second insulator; the sixth insulator includes a region in contact with a top surface of the first insulator, a side surface of the oxide, a side surface and a top surface of the second conductor, and a side surface and a top surface of the third conductor; the first conductor overlaps with the oxide and the fourth conductor; the third insulator overlaps with the oxide and the fourth conductor; the fourth insulator overlaps with the oxide and the second conductor; the fifth insulator overlaps with the oxide and the third conductor; the eighth insulator is in contact with each of a side surface of the third insulator, the side surface of the oxide, and a side surface of the seventh insulator; and a top surface of the third insulator is level or substantially level with a top surface of the fourth insulator and a top surface of the fifth insulator.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first conductive layer with the first insulating layer therebetween. The second insulating layer covers the top surface and a side surface of the second conductive layer. The third conductive layer is positioned over the second insulating layer. The semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second insulating layer, and the third conductive layer. The third insulating layer is positioned over the semiconductor layer. The fourth conductive layer is positioned over the semiconductor layer with the third insulating layer therebetween.

A semiconductor device includes a first gate electrode, a first gate insulating layer, an oxide semiconductor layer, a second gate insulating layer having first and second apertures, a second gate electrode extending in a first direction, a first electrode in contact with the oxide semiconductor layer in the first aperture and a second electrode in contact with the oxide semiconductor layer in the second aperture, wherein the second gate electrode overlaps the oxide semiconductor layer in a first region in a plan view, the first electrode is in contact with the oxide semiconductor layer in a second region in the plan view, a width of the second gate electrode in a second direction is 2 m or less in a cross-sectional view, and a distance between the first region and the second region in the second direction is 2 m or less in the cross-sectional view.

MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.