A semiconductor device including a transistor having a minute size is provided. In the semiconductor device, a second conductive layer is provided over a first conductive layer; the second conductive layer has a first opening overlapping with the first conductive layer; a third conductive layer is provided over the second conductive layer; the third conductive layer has a second opening overlapping with the first opening; a first insulating layer is in contact with a sidewall of the first opening in the second conductive layer; a semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface of the third conductive layer; a second insulating layer is provided over the semiconductor layer; a fourth conductive layer is provided over the second insulating layer; the first insulating layer includes a region sandwiched between the sidewall of the first opening in the second conductive layer and the semiconductor layer; and the semiconductor layer includes a region sandwiched between the sidewall of the first opening in the second conductive layer and the fourth conductive layer.

A semiconductor device having a high degree of integration is provided. A first and second transistors which are electrically connected to each other and a first insulating layer are included. The first transistor includes a first semiconductor layer, a second insulating layer, and a first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and a fourth to sixth conductive layers. The first insulating layer is positioned over the first conductive layer and includes an opening reaching the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer is positioned over the second insulating layer to overlap with the inner wall of the opening. The third insulating layer is positioned over the fourth conductive layer. The fifth and sixth conductive layers are positioned over the fourth conductive layer with the third insulating layer therebetween. The second semiconductor layer is in contact with top surfaces of the fifth and sixth conductive layers, side surfaces thereof that face each other, and a top surface of the third insulating layer sandwiched between the fifth conductive layer and the sixth conductive layer.

The present disclosure provides a semiconductor device and a method for preparing same. The semiconductor device includes a substrate, a source, a semiconductor layer, a drain, an insulating layer, and a gate. A main body portion of the source and a main body portion of the drain are disposed on different faces. The semiconductor layer is disposed between the source and the drain. The gate is disposed on a side of the semiconductor layer. Therefore, a vertical channel thin film transistor (TFT) is formed. In this way, the mobility of carriers in the TFT and the performance of the semiconductor device are effectively improved.

Provided are semiconductor devices and methods of manufacturing the semiconductor device. The semiconductor device includes a lower electrode, a channel on the lower electrode and including an oxide semiconductor, an upper electrode on the channel and including tungsten or molybdenum, a first interlayer between the lower electrode and the channel, and a second interlayer between the channel and the upper electrode, wherein the channel has a vertical channel structure extending in a vertical direction from the lower electrode to the upper electrode, and the first interlayer and the second interlayer include different materials.

An array substrate and a display panel are disclosed. The array substrate includes a substrate, a first conductor portion located at a side of the substrate, a second conductor portion, and an active layer. The active layer includes a first doped portion, a second doped portion and a channel portion, the second doped portion is located at a side of the first doped portion away from the substrate, the channel portion is connected between the first doped portion and the second doped portion, the first conductor portion is contact with the first doped portion, and the second conductor portion is contact with the second doped portion.

A semiconductor device including a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer in contact with the first conductive layer and the second conductive layer, a third conductive layer over the first insulating layer, a semiconductor layer in contact with the third conductive layer, the first conductive layer, and the first insulating layer, a second insulating layer over the first insulating layer, the semiconductor layer, and the third conductive layer, and a fourth conductive layer over the second insulating layer is provided. A shortest distance from a top surface of the first conductive layer to a top surface of the second conductive layer is longer than a shortest distance from the top surface of the first conductive layer to a bottom surface of the fourth conductive layer.

The present disclosure provides a thin film transistor and a method of manufacturing a thin film transistor. The thin film transistor includes a first conductive layer, an isolation layer and a semiconductor layer. The isolation layer is formed on a side of the first conductive layer, the isolation layer includes a body portion and a buffer portion that are arranged continuously, the body portion includes a first surface away from and in parallel to the first conductive layer, and a thickness of the buffer portion gradually decreases from a side close to the body portion to a side away from the body portion. The semiconductor layer includes a first portion and a second portion that are arranged continuously, the first portion is formed on a side of the isolation layer away from the first conductive layer, and the second portion is in contact with the first conductive layer.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first conductive layer with the first insulating layer therebetween. The second insulating layer covers the top surface and a side surface of the second conductive layer. The third conductive layer is positioned over the second insulating layer. The semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second insulating layer, and the third conductive layer. The third insulating layer is positioned over the semiconductor layer. The fourth conductive layer is positioned over the semiconductor layer with the third insulating layer therebetween.

In a thin-film transistor device, an inorganic insulating layer covers the via wall of a via, an active layer is disposed on a first electrode, the inorganic insulating layer, and a second electrode, a gate insulating layer covers the active layer, and a gate is disposed on a side of the gate insulating layer away from the via wall of the via, where the first electrode, the second electrode, and the inorganic insulating layer have the same conductive element.

The present disclosure relates to a vertical gate-all-around thin film transistor and a method of manufacturing a vertical gate-all-around thin film transistor. The vertical gate-all-around thin film transistor includes a substrate; an isolation layer on the substrate; a source layer on the isolation layer; an annular thin film channel on the source layer; a drain layer on an upper part of the annular thin film channel; and a vertical surrounding gate filled on an inner side of the annular thin film channel and covering a sidewall of the annular thin film channel, wherein the substrate, the isolation layer, the source layer, the annular thin film channel, the drain layer, and the vertical surrounding gate are stacked sequentially from bottom to up.