Disclosed are a thin film transistor, a method of manufacturing the same, and an array substrate. The thin film transistor includes a substrate, a gate, a gate insulating layer, an active layer, an ohmic contact layer, and a source-drain electrode layer, the gate insulating layer includes at least a first gate insulating layer deposited at a low rate, a second gate insulating layer deposited at a high rate, and a third gate insulating layer deposited at a low rate, the first gate insulating layer is in contact with the gate, the third gate insulating layer is in contact with the active layer, and the first gate insulating layer and the third gate insulating layer have a density greater than a density of the second gate insulating layer.

Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

A display apparatus includes a substrate, a gate electrode overlapping the substrate, and a semiconductor layer positioned between the substrate and the gate electrode. The semiconductor layer includes a first layer and a second layer positioned between the first layer and the gate electrode. A hydrogen content of the first layer is greater than a hydrogen content of the second layer.

A method of manufacturing a display device according to an embodiment of the present invention includes forming amorphous silicon on a substrate and forming a conductive protective layer on the amorphous silicon, doping with fluorine and removing the conductive protective layer.

A semiconductor device including an oxide semiconductor layer which is formed over a substrate and includes indium is provided. The oxide semiconductor layer is formed in parallel or substantially in parallel with a surface of the substrate. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a formation surface of the oxide semiconductor layer to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the formation surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formation surface are observed in each of the first region, the second region, and the third region.

Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.

An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

A semiconductor device includes a metal oxide layer over an insulating surface and an oxide semiconductor layer over the metal oxide layer. A fluorine concentration of the metal oxide semiconductor layer is greater than or equal to 110.sup.18 atoms/cm.sup.3. In a SIMS analysis, a secondary ion intensity of fluorine detected in the metal oxide layer may be greater than or equal to 10 times a secondary ion intensity of fluorine detected in the oxide semiconductor layer.

A semiconductor device according to an embodiment includes: a metal oxide layer above a substrate, the metal oxide layer containing aluminum as a main component; an oxide semiconductor layer above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein the oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.