A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.

A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

This semiconductor device includes a substrate, a channel layer provided on one side of a surface of the substrate and including a first nitride semiconductor having a first bandgap, a barrier layer provided on an opposite side of the channel layer from the substrate and including a second nitride semiconductor that includes Al.sub.x1In.sub.y1Ga.sub.(1x1y1)N (0<x1<1, 0<y1<1) and has a second bandgap larger than the first bandgap of the first nitride semiconductor, and an intermediate layer provided in the barrier layer and including a third nitride semiconductor that includes Al.sub.x2In.sub.y2Ga.sub.(1x2y2)N (0x2<1, 0y2<1), and the semiconductor device satisfies (1x1y1)<(1x2y2).