A nitride semiconductor device includes a SiC substrate having a hexagonal crystal structure and including a main surface inclined with respect to a c-plane at an off-angle from 2 to 6 in a specific crystal direction, a nitride semiconductor layer located on the main surface of the SiC substrate and including an electron transit layer and an electron supply layer, and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The main surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in plan view. The source electrode and the drain electrode are separated in the first direction. The gate electrode extends in the second direction between the source electrode and the drain electrode. The first direction intersects the third direction at an angle of 9015.

A nitride semiconductor device includes a SiC substrate having a hexagonal crystal structure and including a main surface inclined with respect to a c-plane at an off-angle from 2 to 6 in a specific crystal direction, a nitride semiconductor layer located on the main surface of the SiC substrate and including an electron transit layer and an electron supply layer, and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The main surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in plan view. The source electrode and the drain electrode are separated in the first direction. The gate electrode extends in the second direction between the source electrode and the drain electrode. The first direction intersects the third direction at an angle of 9015.

A computing system is presented. The computing system comprises a Majorana island at which a plurality of Majorana zero modes are instantiated, and a grounded region tunably coupled to one of the Majorana zero modes. The grounded region comprises at least a two-dimensional electron gas (2DEG) layer. A first dielectric layer is adjacent to the 2DEG layer. A grounded gate directly contacts the 2DEG layer through a via fill.

A semiconductor device including a substrate including a first region and a second region, a first active pattern extending in a first direction on the first region, a second active pattern extending in the first direction on the second region, a wall structure extending in the first direction between the first region and the second region and separating the first active pattern and the second active pattern from each other, a first gate structure intersecting the first active pattern on the first region, a first two-dimensional (2D) channel layer including a first transition metal dichalcogenide between the first active pattern and the first gate structure, a second gate structure intersecting the second active pattern on the second region, and a second 2D channel layer including a second transition metal dichalcogenide between the second active pattern and the second gate structure may be provided.

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer without penetrating the group III-V barrier layer in the active region.

A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.

A semiconductor structure includes a supporting substrate, a buried layer, a growth substrate, a buffer layer, and a heterojunction structure layer that are sequentially stacked; a plurality of recesses are disposed on a side, away from the supporting substrate, of the growth substrate, and the buffer layer completely covers a surface of the growth substrate. In the present disclosure, the recesses are disposed in the growth substrate, so that a parasitic circuit formed in the growth substrate caused by a radio frequency signal may be blocked, to reduce a disturbance effect of the growth substrate, thereby reducing an RF loss; and the buffer layer is formed, by using epitaxial lateral overgrowth, in the recesses of the growth substrate, so that dislocation density in an epitaxial layer may be greatly reduced, to improve crystal quality, thereby improving characteristics such as electron mobility, breakdown voltage, and leakage current of a device.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices.

A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one intermediate layer. The at least one intermediate layer is formed in such a way that positions of growth of the nanostructures are predetermined on the outer surface of the at least one intermediate layer. At least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures.