A semiconductor device includes: a Si substrate; a back electrode provided below the Si substrate; a SiC layer provided above the Si substrate; a nitride semiconductor layer provided above the SiC layer; a source electrode and a drain electrode provided above the nitride semiconductor layer; a gate electrode in contact with the nitride semiconductor layer; an intermediate layer provided in an opening that creates an opening in the SiC layer and the nitride semiconductor layer; a metal layer provided above the opening so as to cover the intermediate layer; and a conductor that is provided inside a through via that penetrates the intermediate layer and the Si substrate and is electrically connected with the back electrode and the metal layer. The intermediate layer is a metal nitride layer or a silicon oxide layer.

The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

A transistor includes an amorphous substrate, a first buffer layer over the amorphous substrate, a first nitride semiconductor layer in an island-shaped pattern over the first buffer layer, a second nitride semiconductor layer over the first nitride semiconductor layer so as to cover the first nitride semiconductor layer, and a gate electrode layer over the second nitride semiconductor layer so as to overlap the first nitride semiconductor layer.

A nitride semiconductor device includes a first passivation layer and a first field plate electrode arranged on the first passivation layer. The first passivation layer covers an electron supply layer, a gate layer, and a gate electrode. The first field plate electrode includes a plate body and a connector, which electrically connects the plate body and the source electrode. The plate body is at least partially arranged in a region between the gate electrode and the drain electrode in plan view, and extends in a Y-axis direction that is orthogonal to an X-axis direction in plan view. The connector is located above the gate electrode and between the plate body and the source electrode, has a width in the Y-axis direction, and extends in the X-axis direction to connect the plate body and the source electrode.

In an embodiment, a semiconductor substrate is provided that includes a multilayer Group III nitride substrate having a first major surface and at least one heterojunction that is capable of supporting a two-dimensional charge gas. At least one contact includes a contact trench that extends into the multilayer Group III nitride substrate from the first major surface. The contact trench is filled with n-doped Group III nitride material to form an electrical connection to the two-dimensional charge gas. The semiconductor substrate further includes at least one dummy trench extending into the multilayer Group III nitride substrate from the first major surface. The dummy trench is partially filled with n-doped Group III nitride material. The dummy trench has a width B and the contact trench has a width b, where B1.1b.

The invention provides an electronic cascode power device. The electronic cascode power device has a high-side terminal, a low-side terminal and a control terminal. The electronic cascode power device comprises: a high-voltage silicon (Si) super-junction MOSFET with a drain connected to the high-side terminal of the cascode device; a low-voltage gallium nitride (GaN) HEMT with a drain connected to a source of the high-voltage Si super-junction MOSFET, a source connected to the low-side terminal of the cascode device and a gate connected to the control terminal of the cascode device; and an overvoltage clamping circuit connected between the drain and source of the low-voltage GaN HEMT. The provided cascode structure can effectively suppress the reverse-recovery process of super-junction MOSFET, achieving nearly 50% reduction in overall switching loss at high current levels.

A multilayer structure includes an amorphous substrate having an insulating surface, an orientation layer on the amorphous substrate; and a semiconductor pattern containing gallium nitride on the orientation layer, the orientation layer has a first region overlapping the semiconductor pattern and a second region not overlapping the semiconductor pattern. A top surface of the second region is positioned lower than a top surface of the first region. The orientation layer has a groove in the second region that extends from a lower end of the semiconductor pattern to the first region, and in a plan view, the groove overlaps the semiconductor pattern.

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

A group III nitride laminate, including: an underlying substrate; a first layer which is provided on the underlying substrate and contains aluminum nitride; and a second layer which is provided on the first layer and contains gallium nitride, wherein the thickness of the first layer is 11.0 nm or more, and in a region corresponding to a thickness of the first layer, an AlN abundance ratio, which is a ratio of the amount of the aluminum nitride to the total amount of the aluminum nitride and the gallium nitride is less than 78%.

A method for manufacturing a semiconductor device comprising: providing a layered structure of the semiconductor device, the layered structure comprising a first layer, the first layer comprising a III-V compound semiconductor material; depositing a second layer on a main surface region of the first layer such that the second layer comprises silicon and a doping material for the silicon; activating the second layer to form an ohmic contact between the first layer and the second layer.