A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

A gallium nitride (GaN) transistor which includes a multi-layer/multi-thickness barrier layer formed of segments of progressively increasing thickness between the gate and drain to progressively increase the 2DEG density in the channel from gate to drain. The GaN gate can be formed on the base barrier layer to produce an enhancement mode device with a positive threshold voltage. By forming the gate over a thicker segment of the barrier layer, a GaN transistor with a less positive threshold voltage, or a depletion mode transistor with a negative threshold voltage, can be produced.

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.

A nitride semiconductor device includes an electron transit layer, an electron supply layer disposed on the electron transit layer to generate two-dimensional electron gas in the electron transit layer, a gate layer containing acceptor impurities and disposed on the electron supply layer, a gate electrode contacting the gate layer, a source electrode, and a drain electrode. The gate layer includes a trench that is recessed from an upper surface of the gate layer in a region contacting the gate electrode. The trench includes a trench open end, a trench bottom surface, and a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end.

Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a device structure including a gate and an ohmic contact, and one or more inactive blocks laterally positioned between the gate and the ohmic contact.

A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer without penetrating the group III-V barrier layer in the active region.

An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.